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    • 18. 发明授权
    • Method of forming a contact hole of a semiconductor device
    • 形成半导体器件的接触孔的方法
    • US06838330B2
    • 2005-01-04
    • US10445843
    • 2003-05-28
    • Bong-Ho MoonJu-Yun CheolYong-Sun KoIn-Seak Hwang
    • Bong-Ho MoonJu-Yun CheolYong-Sun KoIn-Seak Hwang
    • H01L21/768H01L21/60H01L21/8238
    • H01L21/02063H01L21/76897
    • A method of forming a contact hole of a semiconductor device that is able to prevent excessive etching of an interlayer dielectric pattern includes forming a gate pattern including a first insulation layer pattern, a conductive layer pattern, a capping insulation layer pattern, and a second insulation layer pattern on a substrate; forming a spacer using an insulating material on a sidewall of the gate pattern; forming an interlayer dielectric on the substrate on which the gate pattern and the spacer are formed; forming a contact hole and an interlayer dielectric pattern for exposing the substrate by etching the interlayer dielectric; forming a liner spacer on a sidewall of the spacer and the interlayer dielectric pattern; and cleaning the resultant structure using a cleaning solution. The cleaning solution preferably includes includes ozone water and hydrogen fluoride (HF).
    • 形成能够防止层间电介质图案的过度蚀刻的半导体器件的接触孔的方法包括形成包括第一绝缘层图案,导电层图案,封盖绝缘层图案和第二绝缘体的栅极图案 层图案; 在所述栅极图案的侧壁上使用绝缘材料形成间隔物; 在其上形成有栅极图案和间隔物的基板上形成层间电介质; 形成用于通过蚀刻所述层间电介质来暴露所述衬底的接触孔和层间电介质图案; 在间隔物的侧壁和层间介质图案上形成衬垫; 并使用清洁溶液清洗所得到的结构。 清洗液最好包括臭氧水和氟化氢(HF)。
    • 19. 发明授权
    • Semiconductor devices having self-aligned contact pads
    • 具有自对准接触焊盘的半导体器件
    • US09240414B1
    • 2016-01-19
    • US14875396
    • 2015-10-05
    • Young-Kuk KimKi-Vin ImHan-Jin LimIn-Seak Hwang
    • Young-Kuk KimKi-Vin ImHan-Jin LimIn-Seak Hwang
    • H01L21/336H01L27/108H01L29/78H01L29/423
    • H01L27/10823H01L21/823437H01L21/823475H01L27/10808H01L27/10855H01L27/10885H01L28/60H01L29/4236H01L29/42364H01L29/7827
    • A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.
    • 半导体器件包括具有限定有源区域的场区域的衬底,衬底中的栅极沟槽和沿第一方向延伸的衬底,相应栅极沟槽中的掩埋栅极,在相应的掩埋栅极上的相应栅极沟槽中的栅极栅极栅极, 所述栅极覆盖栅栏从所述有源区域的顶表面突出并且沿所述第一方向延伸,所述栅极覆盖栅栏中的位线沟槽跨过所述栅极覆盖栅栏并沿垂直于所述第一方向的第二方向延伸的相应位线沟槽, 相应位线沟槽的内壁上的绝缘体结构,堆叠在相应位线沟槽中的绝缘体结构上的位线和位线封接图案,与栅极覆盖栅栏自对准的接触焊盘和相邻位之间的衬底上的绝缘体结构 线路和相应接触焊盘上的电容器的下电极。