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1. 发明申请

US20060270241A1 METHOD OF REMOVING A PHOTORESIST PATTERN AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：移除光电子图案的方法和使用其制造半导体器件的方法
公开(公告)号：US20060270241A1
公开(公告)日：2006-11-30
申请号：US11420943
申请日：2006-05-30
申请人： Kyoung-Chul Kim , Dae-Keun Kang , Se-Ho Cha , In-Seak Hwang , Keum-Joo Lee
发明人： Kyoung-Chul Kim , Dae-Keun Kang , Se-Ho Cha , In-Seak Hwang , Keum-Joo Lee
IPC分类号： B08B3/00 , C23G1/00 , H01L21/302
CPC分类号： H01L21/31138 , B08B7/00 , B08B7/0035 , G03F7/427 , H01L28/91
摘要： In a method of removing a photoresist pattern from a substrate without deteriorating a lower electrode or increasing processing time, ozone gas may be provided onto a substrate on which a photoresist pattern may be formed. An oxidation-decomposition process may be carried out using the ozone gas, to thereby decompose the photoresist pattern on the substrate. The decomposed photoresist pattern may be dissolved into water and removed from the substrate in a rinsing process. Accordingly, a photoresist pattern in an opening having a relatively high aspect ratio may be sufficiently removed from a substrate without deteriorating the lower electrode or increasing processing time.
摘要翻译：在不损坏下电极或增加处理时间的情况下从基板上除去光致抗蚀剂图案的方法中，可以在可以形成光致抗蚀剂图案的基板上提供臭氧气体。可以使用臭氧气体进行氧化分解处理，从而分解基板上的光致抗蚀剂图案。分解的光致抗蚀剂图案可以在漂洗过程中溶解在水中并从基材中除去。因此，具有相对高的纵横比的开口中的光致抗蚀剂图案可以从基板充分地去除而不会使下电极恶化或增加处理时间。

2. 发明授权

US07527921B2 Method of treating and removing a photoresist pattern and method of manufacturing a semiconductor device using the same 有权
标题翻译：处理和除去光致抗蚀剂图案的方法和使用其制造半导体器件的方法
公开(公告)号：US07527921B2
公开(公告)日：2009-05-05
申请号：US11475154
申请日：2006-06-27
申请人： Dae-Hyuk Chung , Dae-Keun Kang , Se-Ho Cha
发明人： Dae-Hyuk Chung , Dae-Keun Kang , Se-Ho Cha
IPC分类号： G03C5/18 , G03C5/26 , B08B3/00
CPC分类号： G03F7/423 , G03F7/422 , H01L21/31133 , H01L21/31138 , H01L27/10814 , H01L27/10855 , H01L28/90
摘要： Example embodiments of the present invention relate to methods of treating and removing a photoresist pattern and a method of manufacturing a semiconductor device using the same. Other example embodiments of the present invention relate to a method of treating a photoresist pattern and a method of removing a photoresist pattern formed using a photoresist composition suitable for argon fluoride (ArF). In a method of removing a photoresist pattern, an ozone vapor including a water vapor and an ozone gas may be provided onto the photoresist pattern to remove a hydrophobic group from a photoresist resin included in the photoresist pattern. A cleaning solution may be provided to make the photoresist pattern water-soluble. A cleaning process may be performed on the photoresist pattern to remove the photoresist pattern. The photoresist pattern may be effectively removed without an increased processing time and/or damage to a substrate.
摘要翻译：本发明的示例性实施方案涉及处理和除去光致抗蚀剂图案的方法以及使用其制造半导体器件的方法。本发明的其它示例性实施方案涉及一种处理光致抗蚀剂图案的方法和使用适用于氟化氩（ArF）的光致抗蚀剂组合物形成的光致抗蚀剂图案的方法。在去除光致抗蚀剂图案的方法中，可以在光致抗蚀剂图案上提供包括水蒸气和臭氧气体的臭氧蒸气以从包含在光致抗蚀剂图案中的光致抗蚀剂树脂除去疏水基团。可以提供清洁溶液以使光致抗蚀剂图案具有水溶性。可以在光致抗蚀剂图案上进行清洁处理以除去光致抗蚀剂图案。可以有效地去除光致抗蚀剂图案，而不会增加处理时间和/或对基板的损坏。

3. 发明申请

US20060292491A1 Method of treating and removing a photoresist pattern and method of manufacturing a semiconductor device using the same 有权
公开(公告)号：US20060292491A1
公开(公告)日：2006-12-28
申请号：US11475154
申请日：2006-06-27
申请人： Dae-Hyuk Chung , Dae-Keun Kang , Se-Ho Cha
发明人： Dae-Hyuk Chung , Dae-Keun Kang , Se-Ho Cha
IPC分类号： G03C1/00
CPC分类号： G03F7/423 , G03F7/422 , H01L21/31133 , H01L21/31138 , H01L27/10814 , H01L27/10855 , H01L28/90
摘要： Example embodiments of the present invention relate to methods of treating and removing a photoresist pattern and a method of manufacturing a semiconductor device using the same. Other example embodiments of the present invention relate to a method of treating a photoresist pattern and a method of removing a photoresist pattern formed using a photoresist composition suitable for argon fluoride (ArF). In a method of removing a photoresist pattern, an ozone vapor including a water vapor and an ozone gas may be provided onto the photoresist pattern to remove a hydrophobic group from a photoresist resin included in the photoresist pattern. A cleaning solution may be provided to make the photoresist pattern water-soluble. A cleaning process may be performed on the photoresist pattern to remove the photoresist pattern. The photoresist pattern may be effectively removed without an increased processing time and/or damage to a substrate.

4. 发明申请

US20130134493A1 VERTICAL CHANNEL MEMORY DEVICES WITH NONUNIFORM GATE ELECTRODES 有权
标题翻译：具有非共振门电极的垂直通道存储器件
公开(公告)号：US20130134493A1
公开(公告)日：2013-05-30
申请号：US13689176
申请日：2012-11-29
申请人： Daehong Eom , Kyunghyun Kim , Kwangsu Kim , Jun-Youl Yang , Se-Ho Cha
发明人： Daehong Eom , Kyunghyun Kim , Kwangsu Kim , Jun-Youl Yang , Se-Ho Cha
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/11582 , H01L29/4234 , H01L29/7926
摘要： A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
摘要翻译：在基板上形成包括交替的绝缘层和牺牲层的模堆。形成延伸穿过模具叠层的绝缘层和牺牲层的垂直沟道区域。栅电极形成在相邻绝缘层之间并且围绕垂直沟道区域。栅电极在靠近绝缘层侧壁的第一位置处具有比在远离绝缘层的侧壁的第二位置更大的厚度。

5. 发明申请

US20130092872A1 COMPOSITIONS FOR ETCHING AND METHODS OF FORMING A SEMICONDUCTOR DEVICE USING THE SAME 有权
公开(公告)号：US20130092872A1
公开(公告)日：2013-04-18
申请号：US13601064
申请日：2012-08-31
申请人： Young-Taek Hong , Jinuk Lee , Junghun Lim , Jaewan Park , Chanjin Jeong , Hoon Han , Seonghwan Park , Yanghwa Lee , Sang Won Bae , Daehong Eom , Byoungmoon Yoon , Jihoon Jeong , Kyunghyun Kim , Kyounghwan Kim , ChangSup Mun , Se-Ho Cha , Yongsun Ko
发明人： Young-Taek Hong , Jinuk Lee , Junghun Lim , Jaewan Park , Chanjin Jeong , Hoon Han , Seonghwan Park , Yanghwa Lee , Sang Won Bae , Daehong Eom , Byoungmoon Yoon , Jihoon Jeong , Kyunghyun Kim , Kyounghwan Kim , ChangSup Mun , Se-Ho Cha , Yongsun Ko
IPC分类号： C09K13/06
CPC分类号： H01L21/02658 , C09K13/04 , C09K13/06 , C23F1/16 , H01L21/31111 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.

6. 发明授权

US10242880B2 Method of wet etching and method of fabricating semiconductor device using the same 有权
公开(公告)号：US10242880B2
公开(公告)日：2019-03-26
申请号：US15645419
申请日：2017-07-10
申请人： Kwangsu Kim , Se-Ho Cha , Yongsun Ko , Keonyoung Kim , Kyunghyun Kim , ChangSup Mun , Choongkee Seong , Sunjoong Song , Jinwoo Lee , Hoon Han
发明人： Kwangsu Kim , Se-Ho Cha , Yongsun Ko , Keonyoung Kim , Kyunghyun Kim , ChangSup Mun , Choongkee Seong , Sunjoong Song , Jinwoo Lee , Hoon Han
IPC分类号： H01L21/311 , H01L21/306 , H01L21/4757 , H01L21/02 , H01L21/67 , H01L27/11582 , H01L27/1157 , H01L27/11565
摘要： Disclosed are a method of wet etching and a method of fabricating a semiconductor device. The wet etching method includes providing a wafer in a process bath and an etchant is accommodated, supplying the process bath with a primary etchant to control a concentration of a specific material in the etchant, supplying the process bath with a first additive to increase the concentration of the specific material in the etchant, and supplying the process bath with a second additive to suppress a defect caused by an increase in the concentration of the specific material in the etchant. The etchant includes at least one, of the primary etchant, the first additive, and the second additive. The first additive and the second additive are separately supplied to the process bath.

7. 发明授权

US08963231B2 Three dimensional semiconductor memory devices and methods of fabricating the same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US08963231B2
公开(公告)日：2015-02-24
申请号：US13401013
申请日：2012-02-21
申请人： Sunghae Lee , Daehong Eom , JinGyun Kim , Daehyun Jang , Kihyun Hwang , Seongsoo Lee , Kyunghyun Kim , Chadong Yeo , Jun-Youl Yang , Se-Ho Cha
发明人： Sunghae Lee , Daehong Eom , JinGyun Kim , Daehyun Jang , Kihyun Hwang , Seongsoo Lee , Kyunghyun Kim , Chadong Yeo , Jun-Youl Yang , Se-Ho Cha
IPC分类号： H01L29/792 , H01L27/115 , H01L29/78
CPC分类号： H01L27/11582 , H01L21/283 , H01L21/311 , H01L27/11556 , H01L29/6653 , H01L29/66553 , H01L29/7827
摘要： Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.
摘要翻译：提供三维半导体存储器件及其制造方法。根据该方法，将牺牲层和绝缘层交替重复堆叠在基板上，并且形成贯穿牺牲层的最上层牺牲层的切割区域。切割区域填充有非牺牲层。将绝缘层和牺牲层图案化以形成模具图案。模具图案包括切割区域中的绝缘图案，牺牲图案和非牺牲层。牺牲图案可以用电极代替。还提供了相关的半导体存储器件。

8. 发明申请

US20140004676A1 VERTICAL CHANNEL MEMORY DEVICES WITH NONUNIFORM GATE ELECTRODES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有非共振门电极的垂直通道存储器件及其制造方法
公开(公告)号：US20140004676A1
公开(公告)日：2014-01-02
申请号：US14020192
申请日：2013-09-06
申请人： Daehong Eom , Kyunghyun Kim , Kwangsu Kim , Jun-Youl Yang , Se-Ho Cha
发明人： Daehong Eom , Kyunghyun Kim , Kwangsu Kim , Jun-Youl Yang , Se-Ho Cha
IPC分类号： H01L29/66
CPC分类号： H01L29/66833 , H01L27/11582 , H01L29/4234 , H01L29/7926
摘要： A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
摘要翻译：在基板上形成包括交替的绝缘层和牺牲层的模堆。形成延伸穿过模具叠层的绝缘层和牺牲层的垂直沟道区域。栅电极形成在相邻绝缘层之间并且围绕垂直沟道区域。栅电极在靠近绝缘层侧壁的第一位置处具有比在远离绝缘层的侧壁的第二位置更大的厚度。

9. 发明申请

US20150162344A1 METHODS OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES 审中-公开
标题翻译：制造三维半导体器件的方法
公开(公告)号：US20150162344A1
公开(公告)日：2015-06-11
申请号：US14621568
申请日：2015-02-13
申请人： Sunghae LEE , Daehong Eom , JinGyun Kim , Daehyun Jang , Kihyun Hwang , Seongsoo Lee , Kyunghyun Kim , Chadong Yeo , Jun-Youl Yang , Se-Ho Cha
发明人： Sunghae LEE , Daehong Eom , JinGyun Kim , Daehyun Jang , Kihyun Hwang , Seongsoo Lee , Kyunghyun Kim , Chadong Yeo , Jun-Youl Yang , Se-Ho Cha
IPC分类号： H01L27/115 , H01L29/66 , H01L21/311 , H01L21/283
CPC分类号： H01L27/11582 , H01L21/283 , H01L21/311 , H01L27/11556 , H01L29/6653 , H01L29/66553 , H01L29/7827
摘要： Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.
摘要翻译：提供三维半导体存储器件及其制造方法。根据该方法，将牺牲层和绝缘层交替重复堆叠在基板上，并且形成贯穿牺牲层的最上层牺牲层的切割区域。切割区域填充有非牺牲层。将绝缘层和牺牲层图案化以形成模具图案。模具图案包括切割区域中的绝缘图案，牺牲图案和非牺牲层。牺牲图案可以用电极代替。还提供了相关的半导体存储器件。

10. 发明授权

US08940182B2 Compositions for etching and methods of forming a semiconductor device using the same 有权
标题翻译：用于蚀刻的组合物和使用其形成半导体器件的方法
公开(公告)号：US08940182B2
公开(公告)日：2015-01-27
申请号：US13601064
申请日：2012-08-31
申请人： Young-Taek Hong , Jinuk Lee , Junghun Lim , Jaewan Park , Chanjin Jeong , Hoon Han , Seonghwan Park , Yanghwa Lee , Sang Won Bae , Daehong Eom , Byoungmoon Yoon , Jihoon Jeong , Kyunghyun Kim , Kyounghwan Kim , ChangSup Mun , Se-Ho Cha , Yongsun Ko
发明人： Young-Taek Hong , Jinuk Lee , Junghun Lim , Jaewan Park , Chanjin Jeong , Hoon Han , Seonghwan Park , Yanghwa Lee , Sang Won Bae , Daehong Eom , Byoungmoon Yoon , Jihoon Jeong , Kyunghyun Kim , Kyounghwan Kim , ChangSup Mun , Se-Ho Cha , Yongsun Ko
IPC分类号： C09K13/06 , C09K13/04 , C23F1/16 , H01L21/311 , H01L29/66 , H01L29/788 , H01L29/792 , H01L27/115
CPC分类号： H01L21/02658 , C09K13/04 , C09K13/06 , C23F1/16 , H01L21/31111 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.
摘要翻译：提供蚀刻组合物。蚀刻组合物包括磷酸，铵离子和硅化合物。硅化合物包括硅原子，具有与硅原子结合的氨基的原子团以及与硅原子结合的至少两个氧原子。还提供了利用蚀刻组合物的方法。

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