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11. 发明申请

US20080089116A1 SRAM voltage control for improved operational margins 有权
公开(公告)号：US20080089116A1
公开(公告)日：2008-04-17
申请号：US11998948
申请日：2007-12-03
申请人： Wayne Ellis , Randy Mann , David Wager , Robert Wong
发明人： Wayne Ellis , Randy Mann , David Wager , Robert Wong
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C5/14 , G11C11/413
摘要： A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected one of the plurality of portions of the SRAM. The power supply voltage to the selected portion is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected portion.

12. 发明申请

US20070164337A1 FLIP FERAM CELL AND METHOD TO FORM SAME 有权
标题翻译：翻转毛细胞及其形成方法
公开(公告)号：US20070164337A1
公开(公告)日：2007-07-19
申请号：US11687000
申请日：2007-03-16
申请人： James Adkisson , Charles Black , Alfred Grill , Randy Mann , Deborah Neumayer , Wilbur Pricer , Katherine Saenger , Thomas Shaw
发明人： James Adkisson , Charles Black , Alfred Grill , Randy Mann , Deborah Neumayer , Wilbur Pricer , Katherine Saenger , Thomas Shaw
IPC分类号： H01L29/94
CPC分类号： H01L28/55 , H01L27/0629 , H01L27/11502 , H01L27/11507 , Y10S438/977
摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.
摘要翻译：提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。本发明的方法包括分别形成CMOS结构和铁电输送晶片。然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

13. 发明申请

US20050199908A1 METHOD OF BASE FORMATION IN A BICMOS PROCESS 失效
标题翻译： BICMOS过程中基质形成的方法
公开(公告)号：US20050199908A1
公开(公告)日：2005-09-15
申请号：US10708598
申请日：2004-03-13
申请人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
发明人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/417 , H01L29/73 , H01L29/732 , H01L29/737 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

14. 发明申请

US20050148140A1 Method for scalable, low-cost polysilicon capacitor in a planar dram 失效
标题翻译：在平面电极中可扩展的低成本多晶硅电容器的方法
公开(公告)号：US20050148140A1
公开(公告)日：2005-07-07
申请号：US10963228
申请日：2004-10-12
申请人： Jeffrey Brown , Randy Mann
发明人： Jeffrey Brown , Randy Mann
IPC分类号： H01L21/8242 , H01L27/02 , H01L27/12 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/10861 , H01L27/0207 , H01L27/1203
摘要： Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.
摘要翻译：提供了增加电容而不损及电池区的电容器结构及其制造方法。第一电容器结构包括存在于半导体衬底中的孔中的绝缘材料，其中每个电容器孔的底壁上的绝缘材料与每个孔的侧壁相比较厚。在另一个电容器结构中，提供深电容器孔，其具有存在于每个孔下方的隔离植入区。

15. 发明申请

US20050121676A1 FinFET SRAM cell using low mobility plane for cell stability and method for forming 失效
标题翻译： FinFET SRAM单元使用低迁移率平面进行电池稳定性和成型方法
公开(公告)号：US20050121676A1
公开(公告)日：2005-06-09
申请号：US10987532
申请日：2004-11-12
申请人： David Fried , Randy Mann , K. Muller , Edward Nowak
发明人： David Fried , Randy Mann , K. Muller , Edward Nowak
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/12 , H01L29/76
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1203 , H01L29/785 , Y10S257/903
摘要： The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation
摘要翻译：本发明提供了一种用于形成它的器件设计和方法，其导致Fin场效应晶体管具有不同的增益而不会不利地影响器件密度。本发明在低载流子迁移率平面中形成相对较低的增益FinFET晶体管，并在高载流子迁移率平面内形成相对较高的增益FinFET晶体管。如此形成的，在高迁移率平面中形成的FinFET具有比在低迁移率平面中形成的FinFET更高的增益。这些实施例特别适用于静态随机存取存储器（SRAM）单元的设计和制造。在这种应用中，用作转移装置的n型FinFET的主体沿{110}平面形成。用作存储锁存器的n型FinFET和p型FinFET的主体沿{100}形成。如此形成的，传送装置的增益大约是n型存储锁存装置的增益的一半，有利于适当的SRAM操作

16. 发明申请

US20050024113A1 METHODS AND APPARATUS FOR EMPLOYING FEEDBACK BODY CONTROL IN CROSS-COUPLED INVERTERS 失效
标题翻译：在交叉耦合逆变器中采用反馈体控制的方法和装置
公开(公告)号：US20050024113A1
公开(公告)日：2005-02-03
申请号：US10604554
申请日：2003-07-30
申请人： Paul Kartschoke , Stephen Kosonocky , Randy Mann , Norman Rohrer
发明人： Paul Kartschoke , Stephen Kosonocky , Randy Mann , Norman Rohrer
IPC分类号： H03K3/037 , H03K3/356
CPC分类号： H03K3/356104 , H03K3/0375
摘要： In a first aspect, a cross-coupled inverter is provided that includes a first inverter circuit having a first NFET coupled to a first PFET and a second inverter circuit having a second NFET coupled to a second PFET. The second inverter circuit is cross-coupled with the first inverter circuit at a plurality of nodes. The body of at least one of the first NFET, the second NFET, the first PFET and the second PFET is coupled so as to form a feedback path that reduces discharging at one or more of the plurality of nodes in response to a soft error event at the cross-coupled inverter.
摘要翻译：在第一方面，提供一种交叉耦合的反相器，其包括具有耦合到第一PFET的第一NFET的第一反相器电路和具有耦合到第二PFET的第二NFET的第二反相器电路。第二逆变器电路在多个节点处与第一反相器电路交叉耦合。第一NFET，第二NFET，第一PFET和第二PFET中的至少一个的主体被耦合以形成反馈路径，其减少响应于软错误事件的多个节点中的一个或多个的放电在交叉耦合的逆变器。

17. 发明申请

US20050012045A1 DETECTOR FOR ALPHA PARTICLE OR COSMIC RAY 失效
标题翻译： ALPHA颗粒或COSMIC RAY的检测器
公开(公告)号：US20050012045A1
公开(公告)日：2005-01-20
申请号：US10604416
申请日：2003-07-18
申请人： John Fifield , Paul Kartschoke , William KIaasen , Stephen Kosonocky , Randy Mann , Jeffery Oppold , Norman Rohrer
发明人： John Fifield , Paul Kartschoke , William KIaasen , Stephen Kosonocky , Randy Mann , Jeffery Oppold , Norman Rohrer
IPC分类号： G01J1/00 , G11C11/412
CPC分类号： G11C11/4125
摘要： A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches that are used in SRAMs. The redundancy repair latches are normally written once at power-up to record failed latch data and are not normally written again. If one of the latches changes states due to an SER (Soft Error Rate-such as a strike by an alpha particle or cosmic ray) event, the repair data in the redundancy latches of the SRAM would now be incorrectly mapped. The detector circuit and method monitors the latches for the occurrence of an SER event, and responsive thereto issues a reload of the repair data to the redundancy repair latches. A first embodiment of the detector circuit differentially detects the floating voltages of first and second silicon wells during periods of non-operation of the circuits fabricated in the first and second silicon wells. In a second embodiment, a detector circuit monitors the background voltage level of a single silicon well over first and second consecutive periods of time. A second application for the detection circuit is for traditional logic circuits.
摘要翻译：一种用于检测硅阱电压或电流以指示硅阱的α粒子或宇宙射线冲击的检测器电路和方法。本发明的检测电路的一个重要应用是用于SRAM中的冗余修复锁存器。冗余修复锁存器在上电时通常写入一次，以记录失败的锁存数据，并且通常不会再次写入。如果其中一个锁存器由于SER（软错误率（例如α粒子或宇宙射线的击穿））事件而改变状态，则SRAM的冗余锁存器中的修复数据现在将被错误地映射。检测器电路和方法监视锁存器以发生SER事件，并且响应于此，将修复数据重新加载到冗余修复锁存器。检测器电路的第一实施例在第一和第二硅阱中制造的电路的非操作期间差分地检测第一和第二硅阱的浮置电压。在第二实施例中，检测器电路在第一和第二连续时间段内监测单个硅阱的背景电压电平。检测电路的第二个应用是传统的逻辑电路。

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