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1. 发明申请

US20050199908A1 METHOD OF BASE FORMATION IN A BICMOS PROCESS 失效
标题翻译： BICMOS过程中基质形成的方法
公开(公告)号：US20050199908A1
公开(公告)日：2005-09-15
申请号：US10708598
申请日：2004-03-13
申请人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
发明人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/417 , H01L29/73 , H01L29/732 , H01L29/737 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

2. 发明申请

US20060017066A1 Methods of base formation in a BiCMOS process 失效
标题翻译： BiCMOS工艺中碱形成的方法
公开(公告)号：US20060017066A1
公开(公告)日：2006-01-26
申请号：US11231385
申请日：2005-09-21
申请人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
发明人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
IPC分类号： H01L31/109
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

3. 发明申请

US20060081934A1 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 失效
标题翻译：双极晶体管具有可选择的自对准的外部基极和其形成方法
公开(公告)号：US20060081934A1
公开(公告)日：2006-04-20
申请号：US11289915
申请日：2005-11-30
申请人： Marwan Khater , James Dunn , David Harame , Alvin Joseph , Qizhi Liu , Francois Pagette , Stephen Onge , Andreas Stricker
发明人： Marwan Khater , James Dunn , David Harame , Alvin Joseph , Qizhi Liu , Francois Pagette , Stephen Onge , Andreas Stricker
IPC分类号： H01L23/62
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.
摘要翻译：公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。然后通过在第一非本征基层上的光刻形成电介质着色焊盘。接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

4. 发明申请

US20050048735A1 BIPOLAR TRANSISTOR HAVING RAISED EXTRINSIC BASE WITH SELECTABLE SELF-ALIGNMENT AND METHODS OF FORMING SAME 有权
标题翻译：具有可选择的自对准的提升的超级基座的双极晶体管及其形成方法
公开(公告)号：US20050048735A1
公开(公告)日：2005-03-03
申请号：US10604988
申请日：2003-08-29
申请人： Marwan Khater , James Dunn , David Harame , Alvin Joseph , Qizhi Liu , Francois Pagette , Stephen St. Onge , Andreas Stricker
发明人： Marwan Khater , James Dunn , David Harame , Alvin Joseph , Qizhi Liu , Francois Pagette , Stephen St. Onge , Andreas Stricker
IPC分类号： H01L21/331 , H01L29/10 , H01L29/732 , H01L29/737 , H01L21/76
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.
摘要翻译：公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。然后通过在第一非本征基层上的光刻形成电介质着色焊盘。接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

5. 发明申请

US20060289852A1 Bipolar transistor with collector having an epitaxial Si:C region 失效
标题翻译：具有集电极的双极晶体管具有外延Si：C区域
公开(公告)号：US20060289852A1
公开(公告)日：2006-12-28
申请号：US11511047
申请日：2006-08-28
申请人： Gregory Freeman , Marwan Khater , Rajendran Krishnasamy , Kathryn Schonenberg , Andreas Stricker
发明人： Gregory Freeman , Marwan Khater , Rajendran Krishnasamy , Kathryn Schonenberg , Andreas Stricker
IPC分类号： H01L31/00
CPC分类号： H01L29/66068 , H01L29/2003 , H01L29/66242
摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.
摘要翻译：提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

6. 发明申请

US20060154476A1 BIPOLAR TRANSISTOR WITH COLLECTOR HAVING AN EPITAXIAL Si:C REGION 有权
标题翻译：具有收集器的双极晶体管具有外延Si：C区域
公开(公告)号：US20060154476A1
公开(公告)日：2006-07-13
申请号：US10905510
申请日：2005-01-07
申请人： Gregory Freeman , Marwan Khater , Rajendran Krishnasamy , Kathryn Schonenberg , Andreas Stricker
发明人： Gregory Freeman , Marwan Khater , Rajendran Krishnasamy , Kathryn Schonenberg , Andreas Stricker
IPC分类号： H01L21/4763
CPC分类号： H01L29/66068 , H01L29/2003 , H01L29/66242
摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.
摘要翻译：提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

7. 发明申请

US20050082642A1 Bipolar transistor with a very narrow emitter feature 失效
标题翻译：双极晶体管具有非常窄的发射极特性
公开(公告)号：US20050082642A1
公开(公告)日：2005-04-21
申请号：US10978775
申请日：2004-11-01
申请人： Gregory Freeman , Marwan Khater , Francois Pagette , Andreas Stricker
发明人： Gregory Freeman , Marwan Khater , Francois Pagette , Andreas Stricker
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732 , H01L21/8222 , H01L27/082 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/732
摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped intrinsic emitter formed in the surface of the intrinsic base. An etch stop insulator layer overlies the intrinsic base layer above the collector. A base contact layer of a conductive material overlies the etch stop dielectric layer and the intrinsic base layer. A dielectric layer overlies the base contact layer. A wide window extends through the insulator layer and the base contact layer down to the insulator layer. An island or a peninsula is formed in the wide window leaving at least one narrowed window within the wide window, with sidewall spacers in either the wide window or the narrowed window. The narrowed windows are filled with doped polysilicon forming an extrinsic emitter with the intrinsic emitter formed below the extrinsic emitter in the surface of the intrinsic base.
摘要翻译：双重多晶硅，自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面的掺杂本征发射极。蚀刻停止绝缘体层覆盖在收集器上方的本征基极层。导电材料的基极接触层覆盖在蚀刻停止介电层和本征基极层之间。电介质层覆盖在基底接触层上。宽窗口延伸穿过绝缘体层和基底接触层向下延伸到绝缘体层。在宽窗口中形成岛或半岛，在宽窗口内留下至少一个变窄的窗口，在宽窗口或狭窄窗口中具有侧壁间隔物。变窄的窗口填充有掺杂的多晶硅，其形成外部发射极，本征发射极在本征基极表面的外部发射极之下形成。

8. 发明申请

US20060231924A1 BIPOLAR TRANSISTOR STRUCTURE WITH SELF-ALIGNED RAISED EXTRINSIC BASE AND METHODS 有权
标题翻译：具有自对准基极的双极晶体管结构和方法
公开(公告)号：US20060231924A1
公开(公告)日：2006-10-19
申请号：US11169444
申请日：2005-06-29
申请人： Thomas Adam , Kevin Chan , Alvin Joseph , Marwan Khater , Qizhi Liu , Beth Rainey , Kathryn Schonenberg
发明人： Thomas Adam , Kevin Chan , Alvin Joseph , Marwan Khater , Qizhi Liu , Beth Rainey , Kathryn Schonenberg
IPC分类号： H01L21/331 , H01L27/082 , H01L27/102 , H01L31/11
CPC分类号： H01L29/7378 , H01L29/1004 , H01L29/66242 , H01L29/66287
摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.
摘要翻译：本发明包括制造双极晶体管的方法，该双极晶体管在形成连接层之前，将硅锗（SiGe）层或例如高压氧化物（HIPOX）的第三绝缘体层与邻近本征基极的发射极帽顶上相加。该添加允许使用湿蚀刻化学去除连接层，以去除在不使用氧化的情况下形成在发射极帽顶上的多余SiGe或第三绝缘体层。在这种情况下，可以使用氧化物部分（通过沉积氧化物或上述HIPOX层的分离）和氮化物间隔物形成发射极 - 基极隔离。本发明导致较低的热循环，较低的应力水平和对发射极盖层厚度的更多控制，这是第一实施例的缺点。本发明还包括所得到的双极晶体管结构。

9. 发明申请

US20050151225A1 BIPOLAR TRANSISTOR STRUCTURE WITH SELF-ALIGNED RAISED EXTRINSIC BASE AND METHODS 有权
标题翻译：具有自对准的双极晶体管结构
公开(公告)号：US20050151225A1
公开(公告)日：2005-07-14
申请号：US10904482
申请日：2004-11-12
申请人： Thomas Adam , Kevin Chan , Alvin Joseph , Marwan Khater , Qizhi Liu , Beth Rainey , Kathryn Schonenberg
发明人： Thomas Adam , Kevin Chan , Alvin Joseph , Marwan Khater , Qizhi Liu , Beth Rainey , Kathryn Schonenberg
IPC分类号： H01L21/331 , H01L29/10
CPC分类号： H01L29/7378 , H01L29/1004 , H01L29/66242 , H01L29/66287
摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.
摘要翻译：本发明包括制造双极晶体管的方法，该双极晶体管在形成连接层之前，将硅锗（SiGe）层或例如高压氧化物（HIPOX）的第三绝缘体层与邻近本征基极的发射极帽顶上相加。该添加允许使用湿蚀刻化学去除连接层，以去除在不使用氧化的情况下形成在发射极帽顶上的多余SiGe或第三绝缘体层。在这种情况下，可以使用氧化物部分（通过沉积氧化物或上述HIPOX层的分离）和氮化物间隔物形成发射极 - 基极隔离。本发明导致较低的热循环，较低的应力水平和对发射极盖层厚度的更多控制，这是第一实施例的缺点。本发明还包括所得到的双极晶体管结构。

10. 发明申请

US20080078997A1 METHOD FOR FORMING A BIPOLAR TRANSISTOR DEVICE WITH SELF-ALIGNED RAISED EXTRINSIC BASE 有权
标题翻译：形成具有自对准基极化基极的双极晶体管器件的方法
公开(公告)号：US20080078997A1
公开(公告)日：2008-04-03
申请号：US11866440
申请日：2007-10-03
申请人： Marwan Khater
发明人： Marwan Khater
IPC分类号： H01L29/04
CPC分类号： H01L29/7378 , H01L29/1004 , H01L29/41708 , H01L29/42304 , H01L29/66242
摘要： Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-are lithographic patterning. An opening is aligned above the dielectric pad and etched through an isolation oxide layer to an extrinsic base layer. The opening is equal to or greater in size than the dielectric pad. Another smaller opening is etched through the extrinsic base layer to the dielectric pad. A multi-step etching process is used to selectively remove the extrinsic base layer from the surfaces of the dielectric pad and then to selectively remove the dielectric pad. An emitter is then formed in the resulting trench. The resulting transistor structure has a distance between the edge of the lower section of the emitter and the edge of the extrinsic base that is minimized, thereby, reducing resistance.
摘要翻译：公开了制造具有自对准凸起外部基极的双极晶体管的方法的实施例。在该方法中，在具有最小尺寸的基板上形成介质垫，该最小尺寸能够使用当前的光刻图案来生产。开口在电介质垫的上方对准，并通过隔离氧化层蚀刻到外在的基层。开口的尺寸等于或大于电介质垫。通过外部基极层蚀刻另一个较小的开口到电介质垫。使用多步蚀刻工艺来从介电垫的表面选择性地去除非本征基层，然后选择性地去除介电垫。然后在所得沟槽中形成发射极。所得到的晶体管结构在发射极的下部边缘与外部基极的边缘之间具有最小化的距离，从而降低电阻。

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