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11. 发明授权

US4984208A Dynamic read/write memory with improved refreshing operation 失效
标题翻译：动态读/写存储器，具有改进的刷新操作
公开(公告)号：US4984208A
公开(公告)日：1991-01-08
申请号：US364529
申请日：1989-06-12
申请人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
发明人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
IPC分类号： G11C11/403 , G11C11/406
CPC分类号： G11C11/406
摘要： A dynamic read/write memory in which refreshing is performed within a read/write cycle so that write recovery time is not prolonged. A word line corresponding to a current address is continuously rendered operative within a write period. When a write operation is completed, the word line is rendered operative so that refreshing is initiated. A word line is rendered operative only within a given period of a read period.
摘要翻译：动态读/写存储器，其中在读/写周期内执行刷新以使写恢复时间不延长。对应于当前地址的字线在写入周期内连续地进行操作。当写入操作完成时，字线被操作，从而启动刷新。字线只能在读取周期的给定时间段内运行。

12. 发明授权

US4894561A CMOS inverter having temperature and supply voltage variation compensation 失效
标题翻译： CMOS逆变器具有温度和电源电压变化补偿
公开(公告)号：US4894561A
公开(公告)日：1990-01-16
申请号：US256664
申请日：1988-10-13
申请人： Kazutaka Nogami
发明人： Kazutaka Nogami
IPC分类号： H03K17/14 , G05F3/24 , H03K17/04 , H03K17/16 , H03K19/003 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/00384 , G05F3/245
摘要： A semiconductor integrated circuit comprises a pair of P-channel and N-channel MOS output transistors connected in series between a power source voltage node and a ground node, a first logic circuit for controlling a gate potential of the P-channel MOS output transistor, a first current control circuit for controlling a current flowing into a ground potential path of the first logic circuit, a second logic circuit for controlling a gate potential of the N-channel MOS output transistor, a second current control circuit for controlling a current flowing into a power source potential path of the second logic circuit, and the first and second current control circuits having a current-temperature characteristic and a current-power source voltage characteristic which are inversely proportional to those of the MOS output transistors. With such an arrangement, the power source voltage dependency and the temperature dependency of the MOS output transistors are cancelled out by the control currents of the first and second current control circuits. Thus, the output voltage of the output circuit depends little on the change of the power source voltage and the operating temperature.
摘要翻译：半导体集成电路包括串联连接在电源电压节点和接地节点之间的一对P沟道和N沟道MOS输出晶体管，用于控制P沟道MOS输出晶体管的栅极电位的第一逻辑电路，用于控制流入第一逻辑电路的地电位路径的电流的第一电流控制电路，用于控制N沟道MOS输出晶体管的栅极电位的第二逻辑电路，用于控制流入第二逻辑电路的电源电位路径，以及第一和第二电流控制电路具有与MOS输出晶体管成反比的电流 - 温度特性和电流 - 电源电压特性。通过这样的布置，MOS输出晶体管的电源电压依赖性和温度依赖性被第一和第二电流控制电路的控制电流抵消。因此，输出电路的输出电压几乎不取决于电源电压和工作温度的变化。

13. 发明授权

US4853897A Complementary semiconductor memory device 失效
标题翻译：互补半导体存储器件
公开(公告)号：US4853897A
公开(公告)日：1989-08-01
申请号：US128946
申请日：1987-12-04
申请人： Kazutaka Nogami , Takayasu Sakurai
发明人： Kazutaka Nogami , Takayasu Sakurai
IPC分类号： G11C11/408 , G11C11/4094 , G11C11/4099
CPC分类号： G11C11/4094 , G11C11/4085 , G11C11/4099
摘要： The invention discloses a semiconductor memory device possessing high operational reliability. In the semiconductor memory device according to the invention, a plurality of well regions of a conductivity type different from that of a semiconductor substrate are formed in the semiconductor substrate, and a memory cell array and a bit line driver are formed in other well regions, situated away from each other. With this arrangement, the number of signal lines to be connected to the well region in which the memory cell array is formed can be reduced, and the adverse influence of minority carriers generated upon operation of the bit line driver can be prevented. With this arrangement, well bias can be applied only to memory cell array. As a result, the operational reliability of the semiconductor memory device can be improved.
摘要翻译：本发明公开了具有高操作可靠性的半导体存储器件。在根据本发明的半导体存储器件中，在半导体衬底中形成不同于半导体衬底的导电类型的多个阱区，并且在其它阱区中形成存储单元阵列和位线驱动器，远离彼此。通过这种布置，可以减少要连接到其上形成存储单元阵列的阱区的信号线的数量，并且可以防止在位线驱动器的操作时产生的少数载流子的不利影响。利用这种布置，阱偏压仅可应用于存储单元阵列。结果，可以提高半导体存储器件的操作可靠性。

14. 发明授权

US5577086A Clock signal generation circuit capable of operating at high speed with high frequency 失效
标题翻译：时钟信号发生电路能够高速高频运行
公开(公告)号：US5577086A
公开(公告)日：1996-11-19
申请号：US365479
申请日：1994-12-28
申请人： Yukihiro Fujimoto , Kazutaka Nogami
发明人： Yukihiro Fujimoto , Kazutaka Nogami
IPC分类号： G01R31/28 , H03D13/00 , H03K3/282 , H03L7/089 , H03L7/093 , H03L7/099 , H03L7/10 , H03L7/107 , H03L7/113 , H03D3/24 , H03L7/00
CPC分类号： H03L7/093 , H03K3/2821 , H03L7/0893 , H03L7/099 , H03L7/113 , H03D13/004 , H03L2207/04
摘要： A clock signal generation circuit performs a stable operation with respect to both a high frequency input clock signal and a sufficient low frequency testing clock signal. The circuit includes a phase comparator for generating a phase difference output corresponding to a phase difference between an internal clock signal and a reference clock signal externally supplied; a frequency distinction circuit for generating a frequency change-over signal when a frequency of the reference clock signal is lower than a preset reference signal; a loop filter for generating an output voltage corresponding to the phase difference output and for changing over a filter constant to that for a low frequency corresponding to the frequency change-over signal; and a voltage control oscillator for setting a frequency of the internal clock signal to a frequency corresponding to the output voltage of the loop filter and for decreasing a change amount of an oscillating frequency with respect to an input signal corresponding to the frequency change-over signal.
摘要翻译：时钟信号发生电路相对于高频输入时钟信号和足够的低频测试时钟信号都执行稳定的操作。该电路包括相位比较器，用于产生对应于外部提供的内部时钟信号和参考时钟信号之间的相位差的相位差输出; 频率鉴别电路，用于当所述参考时钟信号的频率低于预设参考信号时产生频率转换信号; 环路滤波器，用于产生对应于相位差输出的输出电压，并将滤波器常数转换成对应于频率转换信号的低频; 以及电压控制振荡器，用于将内部时钟信号的频率设置为与环路滤波器的输出电压相对应的频率，并且用于相对于与频率转换信号相对应的输入信号减小振荡频率的变化量。

15. 发明授权

US5488326A Data output circuit for semiconductor integrated circuit device which prevents current flow from the output to supply voltage 失效
标题翻译：用于半导体集成电路器件的数据输出电路，防止电流从输出端流向电源
公开(公告)号：US5488326A
公开(公告)日：1996-01-30
申请号：US223648
申请日：1994-04-06
申请人： Sumako Shiraishi , Masami Masuda , Kazutaka Nogami
发明人： Sumako Shiraishi , Masami Masuda , Kazutaka Nogami
IPC分类号： H03K17/687 , H03K19/00 , H03K19/017 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/0013 , H03K19/01721
摘要： A data output circuit includes a P-channel transistor having a source connected to a supply voltage terminal V.sub.DD and a gate coupled to receive a drive signal from an internal circuit, and an N-channel transistor having its drain connected to the drain of the P-channel transistor and its source connected to an output terminal D.sub.out. The threshold voltage of the N-channel transistor is fixed to be lower than the thresholds of other N-channel transistors formed on the same substrate. A high level signal is output from the output terminal D.sub.out when a voltage output by the supply voltage terminal V.sub.DD is supplied to the output terminal D.sub.out through the P-channel transistor and the N-channel transistor. In this configuration; the output terminal charges quickly using the high driving capability of the N-channel transistor. Since the N-channel transistor is interposed along the current path from the output terminal to the supply voltage terminal, current does not flow from the output terminal to the supply voltage terminal when a voltage higher than the supply voltage is applied to the output terminal.
摘要翻译：数据输出电路包括具有连接到电源电压端子VDD的源极的P沟道晶体管和耦合以从内部电路接收驱动信号的栅极，以及其漏极连接到P的漏极的N沟道晶体管通道晶体管，其源极连接到输出端子Dout。 N沟道晶体管的阈值电压被固定为低于在同一衬底上形成的其它N沟道晶体管的阈值。当电源电压端子VDD输出的电压通过P沟道晶体管和N沟道晶体管提供给输出端子Dout时，输出端Dout输出高电平信号。在这种配置中输出端子使用N沟道晶体管的高驱动能力快速充电。由于N沟道晶体管沿着从输出端子到电源电压端子的电流路径插入，所以当高于电源电压的电压被施加到输出端子时，电流不会从输出端子流到电源电压端子。

16. 发明授权

US5479374A Semiconductor memory device employing sense amplifier control circuit and word line control circuit 失效
标题翻译：半导体存储器件采用读出放大器控制电路和字线控制电路
公开(公告)号：US5479374A
公开(公告)日：1995-12-26
申请号：US279684
申请日：1994-07-25
申请人： Tsuguo Kobayashi , Tsukasa Shirotori , Kazutaka Nogami
发明人： Tsuguo Kobayashi , Tsukasa Shirotori , Kazutaka Nogami
IPC分类号： G11C11/419 , G11C7/22 , G11C8/18 , G11C11/407 , G11C11/409 , G11C7/00
CPC分类号： G11C7/22 , G11C8/18
摘要： A semiconductor memory device capable of reducing power consumption has a memory cell array, a plurality of address lines, a pair of data lines, an address transition detector circuit for outputting an address transition signal in response to a change in a signal on the address line, a sense amplifier, a sense amplifier control circuit for activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal, and a word line control circuit which deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.
摘要翻译：能够降低功耗的半导体存储器件具有存储单元阵列，多个地址线，一对数据线，地址转换检测器电路，用于响应于地址线上的信号的变化而输出地址转换信号读出放大器，用于响应于地址转换信号激活读出放大器并响应于读出放大器输出信号去激活读出放大器的读出放大器控制电路，以及禁止对存储器内的字线进行去激活的字线控制电路响应于感测放大器控制电路的单元阵列。

17. 发明授权

US5430391A Data input/output control circuit 失效
标题翻译：数据输入/输出控制电路
公开(公告)号：US5430391A
公开(公告)日：1995-07-04
申请号：US198066
申请日：1994-02-18
申请人： Yukihiro Fujimoto , Tsuguo Kobayashi , Kazutaka Nogami
发明人： Yukihiro Fujimoto , Tsuguo Kobayashi , Kazutaka Nogami
IPC分类号： H03K17/687 , G11C11/409 , H03K19/0175 , H03K19/094 , H03K19/02
CPC分类号： H03K19/09429
摘要： There is disclosed a data input/output control circuit comprising: an input/output circuit for carrying out input of data from the exterior or output of data thereto; and an output circuit such that when the input/output circuit carries out output of data, it delivers, to the input/output circuit, data generated in the exterior and transferred by way of a signal line, while when the input/output circuit carries out input of data, it allows the node between the input/output circuit and the signal line to be placed in high impedance state. In this control circuit, the output circuit includes a switching element and a discharge element connected in series between the signal line and the input/output circuit. The switching element is operative in such a manner that when the input/output circuit carries out output of data, it is closed, while when the input/output circuit carries out input of data, it is opened. In addition, the discharge element is operative in such a manner that when the input/output circuit carries out output of data, it is inoperative, while when the input/output circuit carries out input of data, it discharges the node the switching element and the input/output circuit, thus placing the node between the input/output circuit and signal line in high impedance state.
摘要翻译：公开了一种数据输入/输出控制电路，包括：输入/输出电路，用于从外部输入数据或输出数据; 以及输出电路，使得当输入/输出电路执行数据输出时，它向输入/输出电路传输在外部产生的数据并通过信号线传输，而当输入/输出电路携带输出数据输入，允许输入/输出电路和信号线之间的节点置于高阻态。在该控制电路中，输出电路包括串联连接在信号线与输入/输出电路之间的开关元件和放电元件。开关元件的操作方式是当输入/输出电路执行数据输出时，它被闭合，而当输入/输出电路执行数据输入时，它被打开。此外，放电元件以这样的方式工作，即当输入/输出电路执行数据输出时，它不起作用，而当输入/输出电路执行数据输入时，它将节点放电开关元件和输入/输出电路，从而将节点放置在输入/输出电路与高阻态的信号线之间。

18. 发明授权

US5406511A Mask ROM for storing plural-bit data 失效
标题翻译：用于存储多位数据的掩码ROM
公开(公告)号：US5406511A
公开(公告)日：1995-04-11
申请号：US104443
申请日：1993-08-10
申请人： Kazutaka Nogami
发明人： Kazutaka Nogami
IPC分类号： G11C11/56 , H01L21/8246 , H01L27/112 , G11C11/24
CPC分类号： G11C16/0483 , G11C11/565 , G11C11/5692 , H01L27/112
摘要： Memory cells are formed at mutually facing areas of conductive layers arranged in parallel in a lateral direction and conductive layers arranged in a direction orthogonal to the lateral direction. A plurality of capacitors are formed, as a matrix array, at those mutually facing area of the conductive layers crossing relative to each other in the mutually orthogonal relation. Each capacitor constitutes a memory cell. A plurality of capacity levels, each, are set as a corresponding capacitor level by varying a mutually facing area between the conductive layers.
摘要翻译：存储单元形成在沿横向方向平行布置的导电层的相互面对的区域和沿与横向方向正交的方向布置的导电层。在彼此相交的导电层的相互面对的区域处形成多个电容器作为矩阵阵列。每个电容器构成一个存储单元。通过改变导电层之间相互面对的区域，将多个容量级别设置为相应的电容器电平。

19. 发明授权

US4939695A Virtual type static semiconductor memory device including refresh detector circuitry 失效
标题翻译：包括刷新检测器电路的虚拟型静态半导体存储器件
公开(公告)号：US4939695A
公开(公告)日：1990-07-03
申请号：US268927
申请日：1988-11-09
申请人： Mitsuo Isobe , Takayasu Sakurai , Kazuhiro Sawada , Kazutaka Nogami , Hisashi Ueno
发明人： Mitsuo Isobe , Takayasu Sakurai , Kazuhiro Sawada , Kazutaka Nogami , Hisashi Ueno
IPC分类号： G11C11/403 , G11C11/406
CPC分类号： G11C11/406
摘要： A virtual type static semiconductor memory device according to the present invention comprises a refresh detector circuit for detecting the enabling operation of a refresh control circuit and a terminal for outputting to an outside a detection signal which is generated from the refresh detector circuit. The virtual type static semiconductor memory device informs a present refresh operation to the outside when it is accessed from the outside during the time period in which a refresh operation is conducted in the semiconductor memory device. A system employing the semiconductor memory device allows a slow access at that time only and allows access to be gained to the semiconductor memory device at high speed at other times.

20. 发明授权

US06774679B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06774679B2
公开(公告)日：2004-08-10
申请号：US10333021
申请日：2003-01-15
申请人： Kazutaka Nogami
发明人： Kazutaka Nogami
IPC分类号： G01R2500
CPC分类号： H03K5/26 , H03D13/004 , H03K5/04 , H03L7/0891
摘要： In a semiconductor integrated circuit including a phase comparator circuit for a PLL or DLL, overall lock precision of the PLL or DLL is improved by eliminating a dead zone of the phase comparator circuit and preventing output current offset of a charge pump circuit. The semiconductor integrated circuit includes a first circuit for activating a first phase difference signal corresponding to a phase difference between a first clock signal and a second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first clock signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal, a second circuit for activating a first pulse signal when an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal, a third circuit for combining the first phase difference signal and the first pulse signal, and a fourth circuit for combining the second phase difference signal and the second pulse signal.
摘要翻译：在包括用于PLL或DLL的相位比较器电路的半导体集成电路中，通过消除相位比较器电路的死区并防止电荷泵电路的输出电流偏移来改善PLL或DLL的整体锁定精度。半导体集成电路包括第一电路，用于当第一时钟信号和第二时钟信号的相位延迟超过预定值时与第一时钟信号和第二时钟信号之间的相位差相对应地激活第一相位差信号，第二时钟信号的相位，并且与第二时钟信号的相位相比，当第一时钟信号的相位超过预定值时，激活对应于相位差的第二相位差信号，第二电路用于激活当第一时钟信号的边缘与第二时钟信号的边沿相比延迟时，第一脉冲信号，并且当第二时钟信号的边缘与第二时钟信号的边沿相比第一个时钟信号的边沿被提前时激活第二个脉冲信号用于组合第一相位差信号和第一脉冲信号的第三电路和用于组合t的第四电路他的第二个相位差信号和第二个脉冲信号。

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