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1. 发明授权

US5479374A Semiconductor memory device employing sense amplifier control circuit and word line control circuit 失效
标题翻译：半导体存储器件采用读出放大器控制电路和字线控制电路
公开(公告)号：US5479374A
公开(公告)日：1995-12-26
申请号：US279684
申请日：1994-07-25
申请人： Tsuguo Kobayashi , Tsukasa Shirotori , Kazutaka Nogami
发明人： Tsuguo Kobayashi , Tsukasa Shirotori , Kazutaka Nogami
IPC分类号： G11C11/419 , G11C7/22 , G11C8/18 , G11C11/407 , G11C11/409 , G11C7/00
CPC分类号： G11C7/22 , G11C8/18
摘要： A semiconductor memory device capable of reducing power consumption has a memory cell array, a plurality of address lines, a pair of data lines, an address transition detector circuit for outputting an address transition signal in response to a change in a signal on the address line, a sense amplifier, a sense amplifier control circuit for activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal, and a word line control circuit which deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.
摘要翻译：能够降低功耗的半导体存储器件具有存储单元阵列，多个地址线，一对数据线，地址转换检测器电路，用于响应于地址线上的信号的变化而输出地址转换信号读出放大器，用于响应于地址转换信号激活读出放大器并响应于读出放大器输出信号去激活读出放大器的读出放大器控制电路，以及禁止对存储器内的字线进行去激活的字线控制电路响应于感测放大器控制电路的单元阵列。

2. 发明授权

US5388104A Semiconductor integrated circuit capable of testing memory blocks 失效
标题翻译：能够测试存储器块的半导体集成电路
公开(公告)号：US5388104A
公开(公告)日：1995-02-07
申请号：US813444
申请日：1991-12-26
申请人： Tsukasa Shirotori , Kazutaka Nogami
发明人： Tsukasa Shirotori , Kazutaka Nogami
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/02 , G11C29/12 , G11C29/28 , G11C29/56
CPC分类号： G11C29/28 , G11C29/02
摘要： A semiconductor integrated circuit includes a plurality of writable/readable memory blocks with different address spaces and an address decoder for selecting addresses of the memory blocks. The multiple memory blocks are permitted to share a part of addresses of the memory blocks in a test mode. The writing operation of one of the memory blocks that does not have the largest address space is disabled during a period in which address signals for commonly performing an address scan of individual memory blocks exceeds the address width of that memory block. It is therefore possible to permit a plurality of memory blocks with different address spaces mounted on the same chip to be tested with high precision and without additional burden on the generation of test vectors or on a BIST (built-in self test) test circuit.
摘要翻译：半导体集成电路包括具有不同地址空间的多个可写/可读存储块和用于选择存储块地址的地址解码器。允许多个存储器块在测试模式下共享存储器块的一部分地址。在通常执行各个存储器块的地址扫描的地址信号超过该存储器块的地址宽度的时段期间禁止不具有最大地址空间的存储器块之一的写入操作。因此，可以允许具有安装在同一芯片上的不同地址空间的多个存储块以高精度进行测试，并且不产生测试向量或BIST（内置自检）测试电路的额外负担。

3. 发明授权

US5430391A Data input/output control circuit 失效
标题翻译：数据输入/输出控制电路
公开(公告)号：US5430391A
公开(公告)日：1995-07-04
申请号：US198066
申请日：1994-02-18
申请人： Yukihiro Fujimoto , Tsuguo Kobayashi , Kazutaka Nogami
发明人： Yukihiro Fujimoto , Tsuguo Kobayashi , Kazutaka Nogami
IPC分类号： H03K17/687 , G11C11/409 , H03K19/0175 , H03K19/094 , H03K19/02
CPC分类号： H03K19/09429
摘要： There is disclosed a data input/output control circuit comprising: an input/output circuit for carrying out input of data from the exterior or output of data thereto; and an output circuit such that when the input/output circuit carries out output of data, it delivers, to the input/output circuit, data generated in the exterior and transferred by way of a signal line, while when the input/output circuit carries out input of data, it allows the node between the input/output circuit and the signal line to be placed in high impedance state. In this control circuit, the output circuit includes a switching element and a discharge element connected in series between the signal line and the input/output circuit. The switching element is operative in such a manner that when the input/output circuit carries out output of data, it is closed, while when the input/output circuit carries out input of data, it is opened. In addition, the discharge element is operative in such a manner that when the input/output circuit carries out output of data, it is inoperative, while when the input/output circuit carries out input of data, it discharges the node the switching element and the input/output circuit, thus placing the node between the input/output circuit and signal line in high impedance state.
摘要翻译：公开了一种数据输入/输出控制电路，包括：输入/输出电路，用于从外部输入数据或输出数据; 以及输出电路，使得当输入/输出电路执行数据输出时，它向输入/输出电路传输在外部产生的数据并通过信号线传输，而当输入/输出电路携带输出数据输入，允许输入/输出电路和信号线之间的节点置于高阻态。在该控制电路中，输出电路包括串联连接在信号线与输入/输出电路之间的开关元件和放电元件。开关元件的操作方式是当输入/输出电路执行数据输出时，它被闭合，而当输入/输出电路执行数据输入时，它被打开。此外，放电元件以这样的方式工作，即当输入/输出电路执行数据输出时，它不起作用，而当输入/输出电路执行数据输入时，它将节点放电开关元件和输入/输出电路，从而将节点放置在输入/输出电路与高阻态的信号线之间。

4. 发明授权

US5241510A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5241510A
公开(公告)日：1993-08-31
申请号：US814702
申请日：1991-12-30
申请人： Tsuguo Kobayashi , Kazutaka Nogami
发明人： Tsuguo Kobayashi , Kazutaka Nogami
IPC分类号： G11C11/401 , G11C8/08 , G11C11/00 , G11C11/407 , G11C11/413
CPC分类号： G11C11/005 , G11C8/08
摘要： A semiconductor integrated circuit comprises a plurality of memory blocks each provided with a set of word lines shared by the other memory blocks so that the memory blocks may be accessed separately by using different address signals entered on a time division basis. The integrated circuit also comprises one or more than one decoders for choosing a word line from an end to allow access to any of the plurality of memory blocks and a word line latch circuit inserted into the set of word lines between a pair of memory blocks. With such an arrangement, the number of decoders, word lines, bit lines, memory cells and sense amplifiers as well as the overall size of the integrated circuit can be minimized. Besides, the access time to a certain memory block that constitutes a critical factor to determine the performance the entire integrated circuit can be curtailed so that it may be accessed in a very short period of time and consequently the performance of the circuit may be remarkably improved.
摘要翻译：半导体集成电路包括多个存储块，每个存储块具有由其它存储块共享的一组字线，从而可以通过使用以时分方式输入的不同的地址信号来单独访问存储块。集成电路还包括一个或多于一个解码器，用于从一端选择一个字线，以允许访问多个存储块中的任一个以及插入一对存储块之间的字线组中的字线锁存电路。通过这样的布置，可以使解码器，字线，位线，存储单元和感测放大器的数量以及集成电路的总体尺寸最小化。此外，构成确定整个集成电路的性能的关键因素的某个存储块的访问时间可以被限制，使得其可以在非常短的时间段内被访问，并且因此可以显着地改善电路的性能。

5. 发明授权

US06374281B1 Adder 失效
标题翻译：加法器
公开(公告)号：US06374281B1
公开(公告)日：2002-04-16
申请号：US09258819
申请日：1999-02-26
申请人： Shinji Kitabayashi , Kazutaka Nogami
发明人： Shinji Kitabayashi , Kazutaka Nogami
IPC分类号： G06F750
CPC分类号： G06F7/5318 , G06F7/607 , G06F2207/4818
摘要： An adder comprises: a comparator circuit 2 for comparing values of n input signals, each of which comprises 1-bit data, with first to n-th predetermined values which are different from each other; a non-volatile memory 6 having first to n+1-th word lines, m (2m≧n+1) bit lines which are provided so as to intersect the word lines, and memory cells, each of which is provided at an intersection of each of the word lines and each of the bit lines and each of which has stored 1-bit data; and a selector circuit 4 for selecting one of the n+1 word lines on the basis of n comparison results of the comparator circuit to activate the selected word line. Thus, a plurality of bits are added at high speed.
摘要翻译：加法器包括：比较器电路2，用于将每个包括1位数据的n个输入信号的值彼此不同的第一至第n个预定值进行比较; 具有第一到第n + 1个字线的非易失性存储器6，被设置为与字线相交的m（2m> = n + 1）位线，以及存储单元，每个存储单元设置在每个字线和每个位线的每个都具有存储的1位数据; 以及选择电路4，用于根据比较器电路的n个比较结果来选择n + 1个字线中的一个，以激活所选择的字线。因此，以高速添加多个位。

6. 发明授权

US5748011A Output buffer circuit 失效
标题翻译：输出缓冲电路
公开(公告)号：US5748011A
公开(公告)日：1998-05-05
申请号：US701675
申请日：1996-08-22
申请人： Makoto Takahashi , Kazutaka Nogami
发明人： Makoto Takahashi , Kazutaka Nogami
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/0948 , H03K19/094
CPC分类号： H03K19/00315
摘要： In the output buffer circuit, when an enable signal is inputted to deactivate the main buffer circuit (MB1) and further when a voltage higher than the first supply voltage V.sub.DD is applied to the output terminal (I/O), since the fifth P-type transistor (QP2) is turned on, the voltage at the output terminal is applied to the gate of the third P-type transistor (QP1), so that this transistor (QP1) is perfectly turned off. Therefore, it is possible to prevent unnecessary current from flowing from the output terminal (I/O) to the first supply voltage (V.sub.DD) terminal through the third P-type transistor (QP1). Further, since the sixth P-type transistor (QP4) is turned on, the voltage at the output terminal is applied to the gate of the second P-type transistor (QP6) through the sixth P-type transistor (QP4), so that this transistor (QP6) can be perfectly turned off. Therefore, it is possible to prevent unnecessary current from flowing to the first supply voltage (V.sub.DD) terminal through the first and second P-type transistors (QP5 and QP6). Further, since a voltage higher than the first supply voltage will not be applied to the gate oxide film of the second to sixth P-type transistors all formed on the same N-type substrate, it is possible to prevent the manufacturing process from being complicated.
摘要翻译：在输出缓冲电路中，当输入使能信号以使主缓冲电路（MB1）去激活时，并且当高于第一电源电压VDD的电压施加到输出端（I / O）时，由于第五P- 类型晶体管（QP2）导通，输出端子处的电压被施加到第三P型晶体管（QP1）的栅极，使得该晶体管（QP1）完全截止。因此，可以防止不必要的电流通过第三P型晶体管（QP1）从输出端子（I / O）流向第一电源电压（VDD）端子。此外，由于第六P型晶体管（QP4）导通，所以通过第六P型晶体管（QP4）将输出端子处的电压施加到第二P型晶体管（QP6）的栅极，使得该晶体管（QP6）可以完全关闭。因此，可以防止不必要的电流通过第一和第二P型晶体管（QP5和QP6）流向第一电源电压（VDD）端子。此外，由于高于第一电源电压的电压将不会施加在同一N型衬底上形成的第二至第六P型晶体管的栅极氧化膜上，所以可以防止制造工艺复杂化。

7. 发明授权

US5459342A Field programmable gate array with spare circuit block 失效
标题翻译：具有备用电路块的现场可编程门阵列
公开(公告)号：US5459342A
公开(公告)日：1995-10-17
申请号：US146312
申请日：1993-11-02
申请人： Kazutaka Nogami , Takayasu Sakurai , Fumitoshi Hatori
发明人： Kazutaka Nogami , Takayasu Sakurai , Fumitoshi Hatori
IPC分类号： H01L21/82 , G06F11/20 , H01L27/118 , H03K19/173 , H01L21/70 , H01L27/00 , H03K19/177
CPC分类号： H03K19/17764
摘要： A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at least one interconnection for connecting at least one of the circuit blocks and the at least one spare circuit programmably; and at least one connecting element disposed on the interconnection of the set of interconnections which turns its status from a turned-on state to a turned-off state or vice versa when programmed. When any one of the circuit blocks is defective, since the defective circuit block can be replaced with the spare circuit block, it is possible to retain any desired functions of the logic circuits by programming the connecting means, thus improving the production yield of the field programmable gate array and thereby reducing the manufacturing cost thereof.
摘要翻译：现场可编程门阵列包括：多个具有逻辑电路的电路块; 至少一个具有逻辑电路的备用电路块; 一组互连，其包括至少一个互连，用于可编程地连接至少一个所述电路块和所述至少一个备用电路; 以及至少一个连接元件，其设置在所述一组互连件的互连上，其在编程时将其状态从打开状态转变为关闭状态，反之亦然。当任何一个电路块有缺陷时，由于可以用备用电路块代替有缺陷的电路块，可以通过编程连接装置来保持逻辑电路的所需功能，从而提高了现场的产量可编程门阵列，从而降低其制造成本。

8. 发明授权

US4757217A Refresh operation control circuit for semiconductor device 失效
标题翻译：半导体器件的刷新操作控制电路
公开(公告)号：US4757217A
公开(公告)日：1988-07-12
申请号：US11882
申请日：1987-02-06
申请人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
发明人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
IPC分类号： G11C11/403 , G11C11/406 , H03K3/356
CPC分类号： G11C11/406
摘要： This invention provides a refresh operation control circuit for a semiconductor memory device. Two flip-flop circuits respectively temporarily hold a normal read start command signal and a refresh start command signal generated within the memory device. A normal operation/refresh operation priority determining circuit wherein 2-input logic circuits are cross-connected so that one output in each case of each of these two flip-flop circuits provides one input of the other flip-flop circuit. The priority determining circuit determines the priority of normal read operation and refresh operation in accordance with the logic level relationship of the one inputs. Either control of the start of normal read operation or control of the start of refresh operation is carried out in accordance with the output of this determination.

9. 发明授权

US5986309A Semiconductor integrated circuit apparatus having a plurality of well bias voltage supply circuits 失效
标题翻译：具有多个阱偏压电源电路的半导体集成电路装置
公开(公告)号：US5986309A
公开(公告)日：1999-11-16
申请号：US178365
申请日：1994-01-06
申请人： Yukihiro Fujimoto , Kazutaka Nogami
发明人： Yukihiro Fujimoto , Kazutaka Nogami
IPC分类号： H01L27/08 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/408 , H01L27/02 , H01L27/10 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119
CPC分类号： G11C5/146 , H01L27/0222
摘要： A semiconductor integrated circuit apparatus comprises a semiconductor substrate, a first well region formed in the upper surface of the semiconductor substrate, a first circuit formed in the first well region, first bias voltage supply functions for supplying a bias voltage to the first well region, a second well region formed in the upper surface of the semiconductor substrate such that it does not contact the first well region, a second circuit formed in the second well region, and second bias voltage supply functions for supplying a bias voltage to the second well region.
摘要翻译：半导体集成电路装置包括半导体衬底，形成在半导体衬底的上表面中的第一阱区，形成在第一阱区中的第一电路，用于向第一阱区提供偏置电压的第一偏置电压供应功能，第二阱区，形成在半导体衬底的上表面中，使得其不接触第一阱区，形成在第二阱区中的第二电路和用于向第二阱区域提供偏置电压的第二偏压供应功能。

10. 发明授权

US5764588A Memory circuit 失效
标题翻译：存储电路
公开(公告)号：US5764588A
公开(公告)日：1998-06-09
申请号：US848223
申请日：1997-04-29
申请人： Kazutaka Nogami , Fumitoshi Hatori
发明人： Kazutaka Nogami , Fumitoshi Hatori
IPC分类号： G11C11/41 , G11C7/18 , G11C8/16 , G11C5/06
CPC分类号： G11C8/16 , G11C7/18
摘要： A single-port memory or a multi-port memory with a higher density than conventional memory devices is realized, while using the same design rule, by decreasing the number of bit lines per column or port to decrease the space for wiring and the size of the entire memory. A memory circuit includes a memory cell array arranging a plurality of memory cells in a matrix, each memory cell having at least one read port; word lines each connected to memory cells aligned in a row among the memory cells of the memory cell array, and bit lines each connected to memory cells aligned in n rows (n.gtoreq.2) among the memory cells of the memory cell array. Current drivability of access transistors of memory cells sharing n bit lines are set to satisfy the relation of 1:2: . . . :2.sup.n-1. This results in decreasing the number of bit lines and the area of the memory.
摘要翻译：实现具有比常规存储器件更高密度的单端口存储器或多端口存储器，同时使用相同的设计规则，通过减少每列或端口的位线数量以减少布线空间和尺寸整个记忆存储电路包括以矩阵形式布置多个存储单元的存储单元阵列，每个存储单元具有至少一个读端口; 每个连接到存储单元阵列的存储单元中的一行排列的存储单元的字线以及与存储单元阵列的存储单元中的n行（n> / = 2）对齐的存储单元连接的位线。共享n位线的存储单元的存取晶体管的电流驱动能力设定为满足1：2：的关系。。。：2n-1。这导致位线的数量和存储器的面积减少。

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