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1. 发明授权

US5488326A Data output circuit for semiconductor integrated circuit device which prevents current flow from the output to supply voltage 失效
标题翻译：用于半导体集成电路器件的数据输出电路，防止电流从输出端流向电源
公开(公告)号：US5488326A
公开(公告)日：1996-01-30
申请号：US223648
申请日：1994-04-06
申请人： Sumako Shiraishi , Masami Masuda , Kazutaka Nogami
发明人： Sumako Shiraishi , Masami Masuda , Kazutaka Nogami
IPC分类号： H03K17/687 , H03K19/00 , H03K19/017 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/0013 , H03K19/01721
摘要： A data output circuit includes a P-channel transistor having a source connected to a supply voltage terminal V.sub.DD and a gate coupled to receive a drive signal from an internal circuit, and an N-channel transistor having its drain connected to the drain of the P-channel transistor and its source connected to an output terminal D.sub.out. The threshold voltage of the N-channel transistor is fixed to be lower than the thresholds of other N-channel transistors formed on the same substrate. A high level signal is output from the output terminal D.sub.out when a voltage output by the supply voltage terminal V.sub.DD is supplied to the output terminal D.sub.out through the P-channel transistor and the N-channel transistor. In this configuration; the output terminal charges quickly using the high driving capability of the N-channel transistor. Since the N-channel transistor is interposed along the current path from the output terminal to the supply voltage terminal, current does not flow from the output terminal to the supply voltage terminal when a voltage higher than the supply voltage is applied to the output terminal.
摘要翻译：数据输出电路包括具有连接到电源电压端子VDD的源极的P沟道晶体管和耦合以从内部电路接收驱动信号的栅极，以及其漏极连接到P的漏极的N沟道晶体管通道晶体管，其源极连接到输出端子Dout。 N沟道晶体管的阈值电压被固定为低于在同一衬底上形成的其它N沟道晶体管的阈值。当电源电压端子VDD输出的电压通过P沟道晶体管和N沟道晶体管提供给输出端子Dout时，输出端Dout输出高电平信号。在这种配置中输出端子使用N沟道晶体管的高驱动能力快速充电。由于N沟道晶体管沿着从输出端子到电源电压端子的电流路径插入，所以当高于电源电压的电压被施加到输出端子时，电流不会从输出端子流到电源电压端子。

2. 发明授权

US5400282A Detector circuit for testing semiconductor memory device 失效
标题翻译：用于测试半导体存储器件的检测电路
公开(公告)号：US5400282A
公开(公告)日：1995-03-21
申请号：US914744
申请日：1992-07-17
申请人： Youichi Suzuki , Makoto Segawa , Toshiaki Ohno , Sumako Shiraishi
发明人： Youichi Suzuki , Makoto Segawa , Toshiaki Ohno , Sumako Shiraishi
IPC分类号： G11C29/00 , G01R31/28 , G11C11/413 , G11C29/06 , G11C29/34
CPC分类号： G11C29/34
摘要： A semiconductor memory device having a normal mode of reading and writing data from and to a selected memory cell of a memory cell array. The semiconductor memory device is characterized by control means for switching the normal operation mode to a test mode in response to a test mode signal applied to a certain input terminal, selecting all desired memory cells of the memory cell array at a time, and allowing data applied to a data input terminal to be written to all the selected and desired memory cells at one time.
摘要翻译：具有从存储单元阵列的选定存储单元读取数据的正常模式的半导体存储器件。半导体存储器件的特征在于用于响应于施加到某个输入端子的测试模式信号将正常操作模式切换到测试模式的控制装置，一次选择存储单元阵列的所有期望存储单元，并允许数据一次应用于要写入所有所选存储单元的数据输入端。

3. 发明授权

US5307317A Semiconductor memory device having improved access to addresses 失效
标题翻译：半导体存储器件具有改进的对地址的访问
公开(公告)号：US5307317A
公开(公告)日：1994-04-26
申请号：US726379
申请日：1991-07-05
申请人： Sumako Shiraishi , Youichi Suzuki
发明人： Sumako Shiraishi , Youichi Suzuki
IPC分类号： G11C11/41 , G11C7/10 , H01L27/10 , G11C7/00 , G11C11/42
CPC分类号： G11C7/1048 , G11C7/1051
摘要： One cell of the first cell group CG and one cell of the second cell group CxG are selected simultaneously in response to address signals A1 and A2; data of these selected cells are amplified by the first and second sense amplifiers SA1 and SA2, respectively as sense outputs dA, dA, dB, dB; these sense outputs are given to a select circuit SEL including output buffer circuits OB; the select circuit outputs any of the first and second sense outputs to an output circuit Q17, Q18 in response to select signals ODA, ODB applied from an output switch circuit OSW on the basis of a specific address signal A12, A12. Since plural sense outputs based upon plural cell data are previously outputted simultaneously from the sense amplifiers to the select circuit and then one of the sense outputs is selected on the basis of a specific address, the cell data can be read at high speed as compared with when data are simply read from cells without simultaneous data transfer and data selection.
摘要翻译：响应于地址信号A1和A2，同时选择第一小区组CG的一个小区和第二小区组CxG的一个小区; 这些选择的单元的数据分别由第一和第二读出放大器SA1和SA2放大作为感测输出dA，d（OVS），dB，d（OVS）; 这些感测输出被给予包括输出缓冲电路OB的选择电路SEL; 响应于从输出开关电路OSW基于特定地址信号A12施加的选择信号O（OVS），O（OVS），选择电路将任何第一和第二感测输出输出到输出电路Q17，Q18， A12。由于基于多个单元数据的多个感测输出预先从读出放大器输出到选择电路，然后基于特定地址选择感测输出中的一个，所以可以高速读取单元数据，与当从单元格中简单地读取数据，而不需要同时进行数据传输和数据选择。

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