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11. 发明授权

US06958545B2 Method for reducing wiring congestion in a VLSI chip design 失效
标题翻译：降低VLSI芯片设计中布线拥塞的方法
公开(公告)号：US06958545B2
公开(公告)日：2005-10-25
申请号：US10755590
申请日：2004-01-12
申请人： Pooja M. Kotecha , Rama Gopal Gandham , Ruchir Puri , Louise H. Trevillyan , Adam P. Matheny
发明人： Pooja M. Kotecha , Rama Gopal Gandham , Ruchir Puri , Louise H. Trevillyan , Adam P. Matheny
IPC分类号： G06F17/50 , H01L23/52 , H01L29/40
CPC分类号： G06F17/5077
摘要： A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.
摘要翻译：一种用于校正放置和部分或全部全局路由VLSI芯片设计中的布线拥塞的系统和方法，同时避免添加新的定时或电气违规或其他设计约束。识别全局拥挤区域以及在拥堵区域中确定终止的和未终止的电线。该过程包括优化识别的拥塞区域，逐步重新路由受影响的网络，测试所得到的设计合法性和拥塞度量，以及提交或反转优化和重新排序。优化还包括逻辑单元的移动以及逻辑单元结构（可能与单元移动相结合）的分解，重组或任何其它修改，以将终止的引线移动到较不拥塞的网格边缘，在单元之内或之间重新排列交换连接，或者添加缓冲器引起馈通线的重新路由。

12. 发明申请

US20100042955A1 Method of Minimizing Early-mode Violations Causing Minimum Impact to a Chip Design 有权
标题翻译：最大限度地减少对芯片设计造成最小影响的早期模式违规方法
公开(公告)号：US20100042955A1
公开(公告)日：2010-02-18
申请号：US12191435
申请日：2008-08-14
申请人： POOJA M. KOTECHA , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
发明人： POOJA M. KOTECHA , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.
摘要翻译：一种用于校正在电路设计的处理空间中工作的早期模式定时违反的系统和方法。执行优化来替代在快速路径上增加路径延迟的填充。在处理早期模式违规的设计过程的阶段，假设已经完成了放置，延迟模式定时关闭，路由以及详细的电气和时序分析。优化设计是有效延迟快速路径，同时最大限度地减少对已经完成的芯片上的工作的影响，而不是仅依靠添加可能对所有这些量产生负面影响的焊盘。优化根据其入侵性进行分类，其后进行部署。该部署旨在最大限度地减少使用延迟焊盘，减少设计中断，并尽量减少对设计其他方面的影响。

13. 发明授权

US5257201A Method to efficiently reduce the number of connections in a circuit 失效
标题翻译：有效减少电路中连接数量的方法
公开(公告)号：US5257201A
公开(公告)日：1993-10-26
申请号：US394247
申请日：1989-08-14
申请人： Charles L. Berman , Louise H. Trevillyan
发明人： Charles L. Berman , Louise H. Trevillyan
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/505
摘要： A provided logic circuitry implementation in a given technology includes n signals and m nodes. A final logic circuitry implementation is produced therefrom which is the functional equivalent of, and contains fewer connections than, the provided logic circuitry implementation. A given one of the n signals is first processed, and global information is computed for this signal. A graphical representation of connections between the m nodes is derived from the computed global information. A list of nodes that form a cut-set is produced from the graphical representation, and an optimized logic circuitry implementation is provided as a function thereof. Each of the remaining ones of the n signals are processed sequentially, as above, to form successive optimized logic circuitry implementations, with the processing of the nth signal resulting in the final logic circuitry implementation.
摘要翻译：在给定技术中提供的逻辑电路实现包括n个信号和m个节点。由此产生最终逻辑电路实现，其与所提供的逻辑电路实现的功能等同于并且包含更少的连接。首先对n个信号中的一个信号进行处理，并计算该信号的全局信息。从所计算的全局信息中导出m个节点之间的连接的图形表示。从图形表示产生形成剪切集的节点的列表，并且作为其功能提供优化的逻辑电路实现。如上所述，依次对n个信号中的剩余信号中的每一个进行处理，以形成连续优化的逻辑电路实现，第n个信号的处理产生最终的逻辑电路实现。

14. 发明申请

US20120159418A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH NOTIFICATION OF TRANSFORM SIGNATURES 有权
标题翻译：基于任务的多进程设计合成与变换签名的通知
公开(公告)号：US20120159418A1
公开(公告)日：2012-06-21
申请号：US12972934
申请日：2010-12-20
申请人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
发明人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

15. 发明申请

US20120159406A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH REPRODUCIBLE TRANSFORMS 有权
标题翻译：基于任务的多进程设计与可重构变换的合成
公开(公告)号：US20120159406A1
公开(公告)日：2012-06-21
申请号：US12972980
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.
摘要翻译：基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

16. 发明授权

US07895556B2 Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes 有权
标题翻译：用于优化未路由设计以减少由于耦合和长线路引起的定时问题的概率的方法
公开(公告)号：US07895556B2
公开(公告)日：2011-02-22
申请号：US11942990
申请日：2007-11-20
申请人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
发明人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.
摘要翻译：描述了一种方法和系统，以通过估计由于任何网络上的耦合而可能发生的增量延迟和增量松弛来预测耦合对定时的影响，以便优化以使松弛对潜在耦合违规的灵敏度最小化。本发明可防止有效负载电容的其他意外增加，例如由于意外长的电线路由引起的负载电容。它还估计单个“故障”或“事件”的延迟影响，例如耦合事件或意外长电线路由，包括转换传播的影响。

17. 发明申请

US20090132982A1 METHOD FOR OPTIMIZING AN UNROUTED DESIGN TO REDUCE THE PROBABILITY OF TIMING PROBLEMS DUE TO COUPLING AND LONG WIRE ROUTES 有权
标题翻译：优化设计的方法，以减少因耦合和长途径导致的时序问题的可行性
公开(公告)号：US20090132982A1
公开(公告)日：2009-05-21
申请号：US11942990
申请日：2007-11-20
申请人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
发明人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.
摘要翻译：描述了一种方法和系统，以通过估计由于任何网络上的耦合而可能发生的增量延迟和增量松弛来预测耦合对定时的影响，以便优化以使松弛对潜在耦合违规的灵敏度最小化。本发明可防止有效负载电容的其他意外增加，例如由于意外长的电线路由引起的负载电容。它还估计单个“故障”或“事件”的延迟影响，例如耦合事件或意外长电线路由，包括转换传播的影响。

18. 发明申请

US20080209376A1 SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP 失效
标题翻译： VLSI芯片的关闭时序关闭的系统和方法
公开(公告)号：US20080209376A1
公开(公告)日：2008-08-28
申请号：US11680110
申请日：2007-02-28
申请人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
发明人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.
摘要翻译：一种用于以紧密耦合的递增方式对细节路由网表执行定时优化的方法，其以最小的扰动对放置，路由和断言的寄生信息进行并入，并入统计变异信息，公共路径悲观度降低和电容耦合信息。该方法校正了VLSI电路芯片的放置和路由设计中的违规，其中设计由描述设计的逻辑和物理特性的网表以及对应的时序图表示，该方法包括以下步骤：识别设计; 通过逐步改变设计的逻辑和物理特征，迭代地消除违规行为，仅在设计中纳入合法的布局和路线; 并应用增量时间来评估变革，并更新现有的时间图，以反映由法定刊登位置和路线组成的变更。

19. 发明申请

US20130086537A1 Design Routability Using Multiplexer Structures 失效
标题翻译：使用多路复用器结构设计路由
公开(公告)号：US20130086537A1
公开(公告)日：2013-04-04
申请号：US13248119
申请日：2011-09-29
申请人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
发明人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of the initial logic design representation are identified where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures. Logic elements in the one or more areas of the initial logic design representation are replaced with multiplexer tree structures to generate a modified logic design representation. The modified logic design representation is output to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation.
摘要翻译：提供用于产生集成电路器件的逻辑设计的机构。接收集成电路设备的初始逻辑设计表示，并且识别初始逻辑设计表示的一个或多个区域，其中一个或多个区域中的逻辑元件可被一个或多个多路复用器树结构替代。初始逻辑设计表示的一个或多个区域中的逻辑元件被多路复用器树结构替代以生成修改的逻辑设计表示。经修改的逻辑设计表示被输出到物理合成系统，以基于经修改的逻辑设计表示来生成集成电路器件的物理布局。

20. 发明授权

US08392866B2 Task-based multi-process design synthesis with notification of transform signatures 有权
标题翻译：基于任务的多进程设计综合与转换签名通知
公开(公告)号：US08392866B2
公开(公告)日：2013-03-05
申请号：US12972934
申请日：2010-12-20
申请人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
发明人： Anthony D. Drumm , Frank J. Musante , Jagannathan Narasimhan , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

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