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11. 发明授权

US07206561B2 Radio equipment 失效
标题翻译：无线电设备
公开(公告)号：US07206561B2
公开(公告)日：2007-04-17
申请号：US10399679
申请日：2001-10-19
申请人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
发明人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
IPC分类号： H04B1/06 , H04M1/00 , H05M9/08
CPC分类号： H04B1/40 , H04B1/109 , H04B1/52
摘要： A radio equipment, wherein an attenuator (10) is inserted between antennas (91, 92) and a radio module (2), and output and input sensitivities are raised and lowered simultaneously so as to keep the balance of a radio covering range with an input receiver coverage at a constant, and the antenna (91) and the antenna (92) with attenuator are switched over by a switch (8) to increase and decrease the radio coverage range and input receiver coverage while keeping the balance of the dynamic radio coverage range with the input receiver coverage.
摘要翻译：一种无线电设备，其中在天线（91,92）和无线电模块（2）之间插入衰减器（10），并且输出和输入灵敏度被同时升高和降低，以便将无线电覆盖范围的平衡保持为以恒定的输入接收机覆盖，并且具有衰减器的天线（91）和天线（92）由开关（8）切换，以增加和减少无线电覆盖范围并输入接收机覆盖，同时保持动态无线电的平衡覆盖范围与输入接收机覆盖范围。

12. 发明授权

US06425037B1 Information processing system, bus arbiter, and bus controlling method 有权
标题翻译：信息处理系统，总线仲裁器和总线控制方法
公开(公告)号：US06425037B1
公开(公告)日：2002-07-23
申请号：US09407064
申请日：1999-09-28
申请人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
发明人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. The present invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion means for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage means for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to give a bus occupation right to the bus master.
摘要翻译：本发明提供了一种用于防止诸如通过具有低速IO接入的总线竞争阻塞的主存储访问的事务的执行并提高总线占用效率的手段。本发明包括第一总线，第二总线，多个连接到两个总线的模块，用于在两个总线之间执行信息的协议转换的总线转换装置，用于仲裁总线主机的总线占用权请求的总线仲裁器，以及用于当存储访问数据达到预定量时存储访问数据的存储装置访问目的地是预定模块。每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断其中一个总线主机发出总线占用权请求时，总线仲裁器参考存取装置的访问目的地信息和数据存储状态并决定是否给予巴士总线职业权。

13. 发明授权

US5933623A Synchronous data transfer system 失效
标题翻译：同步数据传输系统
公开(公告)号：US5933623A
公开(公告)日：1999-08-03
申请号：US736212
申请日：1996-10-25
申请人： Masaya Umemura , Toshitsugu Takekuma
发明人： Masaya Umemura , Toshitsugu Takekuma
IPC分类号： G06F13/42 , G06F15/163
CPC分类号： G06F13/4243
摘要： A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit. Each node includes at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit in response to the phase reference signal, and a transfer end signal indicating an end of transferring the data, respectively, in synchronism with the clock signal. A phase reference signal bus is connected to each node. A data bus is connected to each node for transmitting the data and a transfer end signal bus is connected to each node for transmitting the transfer end signal. A sender node includes a sending unit for sending data to a receiver node with a delay after the phase reference signal transmitted to the phase reference signal bus by the sender node, and sending simultaneously the transfer end signal to the receiver node. The receiver node includes a selecting unit for converting the phase reference signal into phase information to select a clock signal having a predetermined phase based on the received clock signal and a receiving unit for receiving data from the sender node using the selected clock signal.
摘要翻译：同步数据传输系统包括振荡电路和连接到振荡电路的多个节点。每个节点至少包括一个内部逻辑电路。每个节点输出指示时钟信号的相位的相位参考信号，响应于相位参考信号由内部逻辑电路处理的数据，以及指示分别传送数据的结束的传送结束信号，与时钟信号。相位参考信号总线连接到每个节点。数据总线连接到每个节点用于发送数据，并且传送结束信号总线连接到每个节点用于发送传送结束信号。发送方节点包括发送单元，用于在发送方节点将相位参考信号发送到相位参考信号总线之后延迟地向接收方节点发送数据，同时将发送结束信号发送到接收方节点。接收器节点包括：选择单元，用于将相位参考信号转换成相位信息，以基于接收到的时钟信号选择具有预定相位的时钟信号;以及接收单元，用于使用所选择的时钟信号从发送器节点接收数据。

14. 发明申请

US20090222798A1 Information Processing Apparatus 审中-公开
标题翻译：信息处理装置
公开(公告)号：US20090222798A1
公开(公告)日：2009-09-03
申请号：US12332397
申请日：2008-12-11
申请人： Shinya IGUCHI , Takatoshi Kato , Masaya Umemura , Nobuaki Kohinata , Yasushi Nagai , Hiroshi Nakagoe , Keitaro Okasaki , Hirotaka Moribe , Takeshi Asahi
发明人： Shinya IGUCHI , Takatoshi Kato , Masaya Umemura , Nobuaki Kohinata , Yasushi Nagai , Hiroshi Nakagoe , Keitaro Okasaki , Hirotaka Moribe , Takeshi Asahi
IPC分类号： G06F9/45
CPC分类号： G06F8/52
摘要： A mobile device includes a memory for storing therein a subroutine management table to manage kinds of existing codes out of native code, first code and second code for a plurality of subroutines contained in content, a virtual machine, a precompile circuit for producing second code from first code and a subroutine management circuit for changing over processing in accordance with the kind of existing code for subroutine called up during execution of content. The subroutine management circuit judges kind of existing code with reference to the subroutine management table when the processing is changed over.
摘要翻译：移动设备包括一个存储器，用于在其中存储子程序管理表以管理内容中的现有代码的种类，用于内容中包含的多个子程序的第一代码和第二代码，虚拟机，用于从第第一代码和子程序管理电路，用于根据在执行内容期间调用的子程序的现有代码的种类来改变处理。当处理转换时，子程序管理电路参考子程序管理表来判断现有代码的种类。

15. 发明授权

US06748463B1 Information processor with snoop suppressing function, memory controller, and direct memory access processing method 失效
标题翻译：具有窥探抑制功能的信息处理器，存储器控制器和直接存储器存取处理方法
公开(公告)号：US06748463B1
公开(公告)日：2004-06-08
申请号：US09463599
申请日：2000-06-22
申请人： Masahide Tsuboi , Takashi Moriyama , Hiroshi Murashima , Masumi Terao , Michinori Naitoh , Koichi Okazawa , Masaya Umemura
发明人： Masahide Tsuboi , Takashi Moriyama , Hiroshi Murashima , Masumi Terao , Michinori Naitoh , Koichi Okazawa , Masaya Umemura
IPC分类号： G06F1314
CPC分类号： G06F12/0835
摘要： An information processing apparatus with a hierarchized bus structure having a system bus connected to central processing units and cache memories and an I/O bus connected to I/O devices. In response to a DMA request from the I/O device, a memory controller connected to both buses and to a main memory compares previous snoop addresses stored in a buffer memory of the memory controller with a current address contained in the DMA request to check whether the current DMA request is coincident with the past snoop process. If the comparison indicates a coincident snoop process, a snoop access process request is inhibited to be output to the system bus and cache memory. With this operation, the number of snoop accesses for DMAs to the same block of the cache memory can be reduced and a time during which the system bus is occupied can be shortened, to thereby improve the system performance.
摘要翻译：具有分级总线结构的信息处理设备，其具有连接到中央处理单元和高速缓冲存储器的系统总线以及连接到I / O设备的I / O总线。响应于来自I / O设备的DMA请求，连接到总线和主存储器的存储器控制器将存储在存储器控制器的缓冲存储器中的先前侦听地址与包含在DMA请求中的当前地址进行比较，以检查是否当前的DMA请求与过去的窥探过程一致。如果比较指示一致的窥探过程，则禁止窥探访问过程请求输出到系统总线和高速缓冲存储器。通过该操作，可以减少DMA到高速缓冲存储器的同一块的窥探访问次数，并且可以缩短系统总线占用的时间，从而提高系统性能。

16. 发明授权

US06438708B1 Information processing apparatus that can hold internal information 有权
标题翻译：可以保存内部信息的信息处理装置
公开(公告)号：US06438708B1
公开(公告)日：2002-08-20
申请号：US09188246
申请日：1998-11-09
申请人： Sawamura Shinichi , Nobuhiko Hara , Jun Kitahara , Masaya Umemura , Masato Ishii , Kenichi Saitou
发明人： Sawamura Shinichi , Nobuhiko Hara , Jun Kitahara , Masaya Umemura , Masato Ishii , Kenichi Saitou
IPC分类号： G06F1132
CPC分类号： G06F1/1616 , G06F1/1677 , G06F1/3203 , G06F9/4418
摘要： An information processing apparatus includes a volatile storage unit and a nonvolatile storage device for storing at least algorithm information for processings executed by the processing unit, processed data inclusive of display-destined data generated in the storage unit and circuit state information concerning individual circuits incorporated in the information processing apparatus during operation of the information processing apparatus, and a control unit for setting a predetermined operation-mode state in accordance with predetermined rules of state transition so as to store selectively the algorithm information, the processed data and the circuit state information in the volatile storage unit and nonvolatile storage device in dependence on the conditions imposed externally through manipulation of the apparatus, whereby the time required for activating or resuming the information processing apparatus is reduced.
摘要翻译：信息处理装置包括易失性存储单元和用于至少存储用于由处理单元执行的处理的算法信息的非易失性存储装置，包括在存储单元中生成的显示目的地数据的处理数据以及包含在其中的各个电路的电路状态信息信息处理装置的操作期间的信息处理装置，以及用于根据预定的状态转换规则设定预定的操作模式状态的控制单元，以选择性地存储算法信息，处理数据和电路状态信息易失性存储单元和非易失性存储设备，这取决于通过操纵设备而外部施加的条件，从而减少了激活或恢复信息处理设备所需的时间。

17. 发明授权

US08413214B2 Terminal system for guaranteeing authenticity, terminal, and terminal management server 失效
标题翻译：终端系统，用于保证真实性，终端和终端管理服务器
公开(公告)号：US08413214B2
公开(公告)日：2013-04-02
申请号：US12709241
申请日：2010-02-19
申请人： Takatoshi Kato , Katsuyuki Umezawa , Makoto Kayashima , Masaya Umemura , Akira Kanehira
发明人： Takatoshi Kato , Katsuyuki Umezawa , Makoto Kayashima , Masaya Umemura , Akira Kanehira
IPC分类号： G06F7/04
CPC分类号： H04L9/3273 , G06F21/31 , G06F2221/2101 , G06F2221/2111 , G06F2221/2129 , H04L9/321
摘要： In a terminal system for managing terminals coupled to a network, a terminal management server includes: a terminal information registration module for registering, in advance, information unique to each user of the terminal; an authentication module for executing authentication by comparing an ID and authentication information which are contained in an authentication request received from the terminal to user information set in advance; an authenticity determination module for determining, based on a predetermined investigation result received from the terminal, whether or not the terminal suffers falsification; and a unique information transmission module for transmitting, when the authentication is successful, and when the authenticity determination module has determined that the terminal does not suffer the falsification, the information unique to the each user to the terminal. The terminal outputs the information unique to the each user received from the terminal management server to a display unit.
摘要翻译：在终端管理服务器的终端系统中，终端管理服务器包括：终端信息登记模块，用于预先登记终端的每个用户唯一的信息; 认证模块，用于通过将从终端接收到的认证请求中包含的ID和认证信息与预先设置的用户信息进行比较来执行认证; 一个真实性确定模块，用于根据终端收到的预定调查结果确定终端是否遭受伪造; 以及唯一的信息传输模块，用于在认证成功时发送，并且当真实性确定模块确定终端没有遭受伪造时，将每个用户唯一的信息发送给终端。终端将从终端管理服务器接收的每个用户唯一的信息输出到显示单元。

18. 发明授权

US06523133B2 Information processing apparatus that can hold internal information 有权
公开(公告)号：US06523133B2
公开(公告)日：2003-02-18
申请号：US10147871
申请日：2002-05-20
申请人： Sawamura Shin'ichi , Nobuhiko Hara , Jun Kitahara , Masaya Umemura , Masato Ishii , Kenichi Saitou
发明人： Sawamura Shin'ichi , Nobuhiko Hara , Jun Kitahara , Masaya Umemura , Masato Ishii , Kenichi Saitou
IPC分类号： G06F1132
CPC分类号： G06F1/1616 , G06F1/1677 , G06F1/3203 , G06F9/4418
摘要： An information processing apparatus includes a volatile storage unit and a nonvolatile storage device for storing at least algorithm information for processings executed by the processing unit, processed data inclusive of display-destined data generated in the storage unit and circuit state information concerning individual circuits incorporated in the information processing apparatus during operation of the information processing apparatus, and a control unit for setting a predetermined operation-mode state in accordance with predetermined rules of state transition so as to store selectively the algorithm information, the processed data and the circuit state information in the volatile storage unit and nonvolatile storage device in dependence on the conditions imposed externally through manipulation of the apparatus, whereby the time required for activating or resuming the information processing apparatus is reduced.

19. 发明授权

US6125419A Bus system, printed circuit board, signal transmission line, series circuit and memory module 失效
标题翻译：总线系统，印刷电路板，信号传输线，串联电路和内存模块
公开(公告)号：US6125419A
公开(公告)日：2000-09-26
申请号：US874721
申请日：1997-06-13
申请人： Masaya Umemura , Hideki Osaka , Toshitsugu Takekuma
发明人： Masaya Umemura , Hideki Osaka , Toshitsugu Takekuma
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4086
摘要： There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.
摘要翻译：提供了多个同步RAM，存储器控制器，用于将从存储器控制器1a输出的信号输入到同步RAM的总线，以及用于将从同步RAM输出的信号输入到存储器控制器的总线。每条公交车都有一条主干线和两根短线连接到树干上。每个同步RAM连接到相应的存根线，使得同步RAM和存储器控制器之间的总线总线长度与同步RAM与存储器控制器之间的总线长度之和基本恒定所有的同步RAM。因此，在多个总线从站之间保持信号传输时间基本恒定的同时，可以缩短总线主机与多个总线从站之间的信号传输时间，而不增加总线主机的引脚数。

20. 发明授权

US6088829A Synchronous data transfer system 有权
标题翻译：同步数据传输系统
公开(公告)号：US6088829A
公开(公告)日：2000-07-11
申请号：US261177
申请日：1999-03-03
申请人： Masaya Umemura , Toshitsugu Takekuma
发明人： Masaya Umemura , Toshitsugu Takekuma
IPC分类号： G06F13/42
CPC分类号： G06F13/4243
摘要： A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit and each including at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit provided internally of the node. The system further includes a transfer end signal indicating an end of the data transfer, in synchronism with the clock signal, and a phase reference signal bus connected to each of the plural nodes, a data bus connected to each of the plural nodes for transmitting the data and a transfer end signal bus connected to each of the plural nodes for transmitting the transfer end signal. A sender node of the plural nodes includes sending unit for sending the data to a receiver node of the plural nodes with a delay relative to the phase reference signal which the sender node itself sent onto the phase reference signal bus while sending simultaneously the transfer end signal to the receiver node, whereas the receiver node includes at least a selecting unit for converting the phase reference signal received into phase information to thereby select a clock signal having a predetermined phase with the clock signal received by the receiver node and a receiving unit for receiving the data from the sender node by using the selected clock signal.
摘要翻译：同步数据传输系统包括振荡电路和连接到振荡电路的多个节点，并且每个节点至少包括一个内部逻辑电路。每个节点输出指示时钟信号相位的相位参考信号，由在节点内部提供的内部逻辑电路处理的数据。该系统还包括与时钟信号同步的表示数据传送结束的传送结束信号和连接到多个节点中的每一个的相位参考信号总线，连接到多个节点中的每一个的数据总线，用于发送数据和连接到多个节点中的每一个的传送结束信号总线，用于发送传送结束信号。多个节点的发送节点包括发送单元，用于将发送方节点本身发送到相位参考信号总线上的相位参考信号延迟地发送到多个节点的接收器节点，同时同时发送传送结束信号而接收机节点至少包括一个选择单元，用于将接收的相位参考信号转换为相位信息，从而选择具有由接收器节点接收的时钟信号的预定相位的时钟信号，以及用于接收的接收单元来自发送方节点的数据通过使用选定的时钟信号。

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