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11. 发明授权

US08614485B2 Process for fabrication of FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US08614485B2
公开(公告)日：2013-12-24
申请号：US12342655
申请日：2008-12-23
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

12. 发明授权

US07037794B2 Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain 失效
标题翻译：提高了用于多栅极氧化和侧壁保护的STI工艺，在应变Si / SGOI结构上具有升高的源极/漏极
公开(公告)号：US07037794B2
公开(公告)日：2006-05-02
申请号：US10709963
申请日：2004-06-09
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

13. 发明授权

US06727141B1 DRAM having offset vertical transistors and method 有权
标题翻译：具有偏移垂直晶体管和方法的DRAM
公开(公告)号：US06727141B1
公开(公告)日：2004-04-27
申请号：US10342419
申请日：2003-01-14
申请人： Gary B. Bronner , Ramachandra Divakaruni , Byeong Kim , Jack A. Mandelman
发明人： Gary B. Bronner , Ramachandra Divakaruni , Byeong Kim , Jack A. Mandelman
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10864 , H01L27/10876
摘要： The distance between buried straps in a DRAM array of trench capacitor/vertical transistor cells is increased by offsetting adjacent cells by a vertical offset distance, so that the total distance between adjacent straps is increased without increasing the horizontal distance between cells.
摘要翻译：沟槽电容器/垂直晶体管单元的DRAM阵列中的埋地带之间的距离通过将相邻单元偏移垂直偏移距离而增加，使得相邻带之间的总距离增加而不增加单元之间的水平距离。

14. 发明授权

US06281064B1 Method for providing dual work function doping and protective insulating cap 失效
标题翻译：提供双功能掺杂和保护绝缘帽的方法
公开(公告)号：US06281064B1
公开(公告)日：2001-08-28
申请号：US09325941
申请日：1999-06-04
申请人： Jack A. Mandelman , Gary B. Bronner , Ramachandra Divakaruni
发明人： Jack A. Mandelman , Gary B. Bronner , Ramachandra Divakaruni
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L27/10873 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A method for providing dual work function doping and borderless array diffusion contacts includes providing a semiconductor substrate, a gate insulator, a conductor on the gate insulator, an insulating cap on the conductor and insulating spacers on sidewalls of a portion of the conductor and the insulating cap. The method also includes doping portions of the semiconductor substrate and the conductor with a first conductive type and other portions with a second conductive type. The conductor may be annealed such that dopants of the first and second conductive types spread over the respective conductors.
摘要翻译：一种用于提供双工作功能掺杂和无边界阵列扩散接触的方法包括提供半导体衬底，栅极绝缘体，栅极绝缘体上的导体，导体上的绝缘帽和导体的一部分的侧壁上的绝缘衬垫和绝缘帽。该方法还包括以第一导电类型和具有第二导电类型的其它部分掺杂半导体衬底和导体的部分。导体可以退火，使得第一和第二导电类型的掺杂物分布在相应的导体上。

15. 发明授权

US06214686B1 Spatially offset deep trenches for high density DRAMS 失效
标题翻译：高密度DRAMS的深沟槽空间偏移
公开(公告)号：US06214686B1
公开(公告)日：2001-04-10
申请号：US09388170
申请日：1999-09-01
申请人： Ramachandra Divakaruni , Gary B. Bronner
发明人： Ramachandra Divakaruni , Gary B. Bronner
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L21/3065 , H01L21/308 , H01L21/76232 , H01L29/66181 , H01L29/945
摘要： A method of forming spatially offset storage nodes for deep trench-based DRAMs on a semiconductor substrate. The method involves etching trenches in the surface of the substrate, masking adjacent trenches with a resist material, etching exposed trenches to a depth of about 1 micron. Removing the masking and etching all the trenches to form bulbulous regions in the sidewall of the trenches. The adjacent trenches having vertically spaced bulbulous regions are filled with dielectric material to form high capacitance storage nodes.
摘要翻译：一种在半导体衬底上形成深沟槽DRAM的空间偏移存储节点的方法。该方法包括蚀刻衬底的表面中的沟槽，用抗蚀剂材料掩蔽相邻的沟槽，将暴露的沟槽蚀刻到约1微米的深度。去除掩模并蚀刻所有沟槽以在沟槽的侧壁中形成凸起区域。具有垂直间隔开的膨胀区域的相邻沟槽用电介质材料填充以形成高电容存储节点。

16. 发明申请

US20090101995A1 PROCESS FOR FABRICATION OF FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US20090101995A1
公开(公告)日：2009-04-23
申请号：US12342655
申请日：2008-12-23
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

17. 发明授权

US6063657A Method of forming a buried strap in a DRAM 失效
标题翻译：在DRAM中形成掩埋带的方法
公开(公告)号：US6063657A
公开(公告)日：2000-05-16
申请号：US255535
申请日：1999-02-22
申请人： Gary B. Bronner , Ramachandra Divakaruni
发明人： Gary B. Bronner , Ramachandra Divakaruni
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： A method and structure for forming a buried strap in a dynamic random access memory structure. The method includes forming a trench adjacent a pass transistor of the dynamic random access memory structure, partially filling the trench with a conductor, forming a collar surrounding an upper portion of the conductor, forming a spacer in a portion of the trench above the conductor, forming an insulator in a remainder of the upper portion of the trench, forming a shallow trench isolation region on one side of the trench opposite the pass transistor, removing the spacer to form a gap between the insulator and the pass transistor, and filling the gap with a conductor to form the buried strap.
摘要翻译：一种用于在动态随机存取存储器结构中形成掩埋带的方法和结构。该方法包括在动态随机存取存储器结构的通过晶体管附近形成沟槽，用导体部分地填充沟槽，形成围绕导体的上部的环形，在导体上方的沟槽的一部分中形成间隔物，在沟槽的上部的其余部分形成绝缘体，在与沟道晶体管相对的沟槽的一侧上形成浅沟槽隔离区，去除间隔物以在绝缘体和传输晶体管之间形成间隙，并填充间隙用导体形成埋地带。

18. 发明授权

US07737502B2 Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain 有权
标题翻译：用于提高源/漏极的应变Si / SGOI结构上的多栅极氧化和侧壁保护的提高的STI工艺
公开(公告)号：US07737502B2
公开(公告)日：2010-06-15
申请号：US11351801
申请日：2006-02-10
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
IPC分类号： H01L27/088
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

19. 发明授权

US07470570B2 Process for fabrication of FinFETs 有权
标题翻译： FinFET的制造工艺
公开(公告)号：US07470570B2
公开(公告)日：2008-12-30
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

20. 发明申请

US20080111184A1 PROCESS FOR FABRICATION OF FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US20080111184A1
公开(公告)日：2008-05-15
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

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