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1. 发明授权

US07737502B2 Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain 有权
标题翻译：用于提高源/漏极的应变Si / SGOI结构上的多栅极氧化和侧壁保护的提高的STI工艺
公开(公告)号：US07737502B2
公开(公告)日：2010-06-15
申请号：US11351801
申请日：2006-02-10
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
IPC分类号： H01L27/088
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

2. 发明授权

US07037794B2 Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain 失效
标题翻译：提高了用于多栅极氧化和侧壁保护的STI工艺，在应变Si / SGOI结构上具有升高的源极/漏极
公开(公告)号：US07037794B2
公开(公告)日：2006-05-02
申请号：US10709963
申请日：2004-06-09
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

3. 发明授权

US07470570B2 Process for fabrication of FinFETs 有权
标题翻译： FinFET的制造工艺
公开(公告)号：US07470570B2
公开(公告)日：2008-12-30
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

4. 发明申请

US20080111184A1 PROCESS FOR FABRICATION OF FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US20080111184A1
公开(公告)日：2008-05-15
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

5. 发明申请

US20090101995A1 PROCESS FOR FABRICATION OF FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US20090101995A1
公开(公告)日：2009-04-23
申请号：US12342655
申请日：2008-12-23
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

6. 发明授权

US08614485B2 Process for fabrication of FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US08614485B2
公开(公告)日：2013-12-24
申请号：US12342655
申请日：2008-12-23
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

7. 发明申请

US20050277271A1 RAISED STI PROCESS FOR MULTIPLE GATE OX AND SIDEWALL PROTECTION ON STRAINED Si/SGOI STRUCTURE WITH ELEVATED SOURCE/DRAIN 失效
标题翻译：用于高压源/排水的应变Si / SGOI结构的多栅极氧化物和栅极保护的提高过程
公开(公告)号：US20050277271A1
公开(公告)日：2005-12-15
申请号：US10709963
申请日：2004-06-09
申请人： Jochen Beintner , Gary Bronner , Ramachandra Divakaruni , Byeong Kim
发明人： Jochen Beintner , Gary Bronner , Ramachandra Divakaruni , Byeong Kim
IPC分类号： C30B1/00 , H01L21/20 , H01L21/336 , H01L21/36 , H01L21/762 , H01L29/10 , H01L29/51 , H01L29/786
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

8. 发明授权

US06759291B2 Self-aligned near surface strap for high density trench DRAMS 失效
标题翻译：用于高密度沟槽DRAMS的自对准近表面带
公开(公告)号：US06759291B2
公开(公告)日：2004-07-06
申请号：US10045499
申请日：2002-01-14
申请人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
发明人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
IPC分类号： H01L218234
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.
摘要翻译：一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形形结构。此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

9. 发明授权

US06369419B1 Self-aligned near surface strap for high density trench DRAMS 失效
标题翻译：用于高密度沟槽DRAMS的自对准近表面带
公开(公告)号：US06369419B1
公开(公告)日：2002-04-09
申请号：US09603657
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
发明人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
IPC分类号： H01L2994
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.
摘要翻译：一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形形结构。此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

10. 发明授权

US6143599A Method for manufacturing memory cell with trench capacitor 有权
标题翻译：具有沟槽电容器的存储单元的制造方法
公开(公告)号：US6143599A
公开(公告)日：2000-11-07
申请号：US235621
申请日：1999-01-22
申请人： Byeong Y. Kim , Carl Radens , Jochen Beintner
发明人： Byeong Y. Kim , Carl Radens , Jochen Beintner
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867
摘要： A memory cell includes a transistor and a capacitor that is a doped polysilicon filled trench. A doped polycrystalline strap provides a low resistance connection between a source region of the transistor and the polysilicon fill and is shaped to overlie both a top surface and a side surface of the source region of the transistor.
摘要翻译：存储单元包括晶体管和作为掺杂多晶硅填充沟槽的电容器。掺杂的多晶带提供了晶体管的源极区域和多晶硅填充物之间的低电阻连接，并且被成形为覆盖晶体管的源极区域的顶表面和侧表面。

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