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11. 发明授权

US07459323B2 Method of manufacturing a thin film transistor array panel 有权
标题翻译：制造薄膜晶体管阵列面板的方法
公开(公告)号：US07459323B2
公开(公告)日：2008-12-02
申请号：US11512805
申请日：2006-08-30
申请人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
发明人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
IPC分类号： H01L21/00
CPC分类号： G02F1/1368 , G02F1/1339
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

12. 发明申请

US20080093600A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20080093600A1
公开(公告)日：2008-04-24
申请号：US11958230
申请日：2007-12-17
申请人： Min-Wook PARK , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , Sang-Jin Jeon
发明人： Min-Wook PARK , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , Sang-Jin Jeon
IPC分类号： H01L29/04
CPC分类号： H01L29/41733 , H01L27/124
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

13. 发明申请

US20060289965A1 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060289965A1
公开(公告)日：2006-12-28
申请号：US11512805
申请日：2006-08-30
申请人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
发明人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： G02F1/1368 , G02F1/1339
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

14. 发明授权

US07119368B2 Thin film transistor array panel and manufacturing method thereof 有权
公开(公告)号：US07119368B2
公开(公告)日：2006-10-10
申请号：US10926719
申请日：2004-08-26
申请人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
发明人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
IPC分类号： H01L31/0376
CPC分类号： G02F1/1368 , G02F1/1339
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

15. 发明申请

US20050110014A1 Thin film transistor array panel and manufacturing method thereof 有权
公开(公告)号：US20050110014A1
公开(公告)日：2005-05-26
申请号：US10922343
申请日：2004-08-19
申请人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , Sang-Jin Jeon
发明人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , Sang-Jin Jeon
IPC分类号： G02F1/1339 , G02F1/136 , G02F1/1368 , G09F9/00 , G09F9/30 , H01L21/00 , H01L21/3205 , H01L21/3213 , H01L21/336 , H01L21/77 , H01L21/84 , H01L23/52 , H01L29/417 , H01L29/786 , H01L31/036
CPC分类号： H01L29/41733 , H01L27/124
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

16. 发明授权

US06524876B1 Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US06524876B1
公开(公告)日：2003-02-25
申请号：US09545891
申请日：2000-04-07
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
IPC分类号： H01L2100
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

17. 发明授权

US07507994B2 Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07507994B2
公开(公告)日：2009-03-24
申请号：US11625694
申请日：2007-01-22
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Hao , Jong-Soo Yoon , Doug-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Hao , Jong-Soo Yoon , Doug-Gyu Kim
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。

18. 发明申请

US20070126005A1 THIN FILM TRANSISTOR ARRAY PANELS FOR A LIQUID CRYSTAL DISPLAY AND A METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列及其制造方法
公开(公告)号：US20070126005A1
公开(公告)日：2007-06-07
申请号：US11625694
申请日：2007-01-22
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Doug-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Doug-Gyu Kim
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。

19. 发明申请

US20050170592A1 Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20050170592A1
公开(公告)日：2005-08-04
申请号：US11080612
申请日：2005-03-16
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Huh , Jong-Soo Yoon , Dong-Gyu Kim
IPC分类号： G02F1/1362 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/49 , H01L31/0376
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

20. 发明授权

US07176496B2 Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07176496B2
公开(公告)日：2007-02-13
申请号：US11080612
申请日：2005-03-16
申请人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Hao , Jong-Soo Yoon , Dong-Gyu Kim
发明人： Bum-Ki Baek , Mun-Pyo Hong , Jang-Soo Kim , Sung-Wook Hao , Jong-Soo Yoon , Dong-Gyu Kim
IPC分类号： H01L29/04 , H01L29/15 , H01L31/36
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , G02F2001/136236 , G02F2001/136272 , G02F2001/13629 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66765 , Y10S438/949
摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.
摘要翻译：包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘，以及在基板上的栅电极。此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。依次形成栅极绝缘层，半导体层和欧姆接触层。导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

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