专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07999707B2 Apparatus for compensating for error of time-to-digital converter 有权
标题翻译：用于补偿时间 - 数字转换器误差的装置
公开(公告)号：US07999707B2
公开(公告)日：2011-08-16
申请号：US12629020
申请日：2009-12-01
申请人： Mi Jeong Park , Byung Hun Min , Ja Yol Lee , Hyun Kyu Yu
发明人： Mi Jeong Park , Byung Hun Min , Ja Yol Lee , Hyun Kyu Yu
IPC分类号： H03M1/06
CPC分类号： G04F10/06 , H03L7/085 , H03L2207/50
摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.
摘要翻译：公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间分辨率提高N倍（N是自然数）。该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一至第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

12. 发明授权

US07933369B2 Apparatus for automatic gain control and wireless receiver employing the same 失效
标题翻译：用于自动增益控制的装置和采用该装置的无线接收器
公开(公告)号：US07933369B2
公开(公告)日：2011-04-26
申请号：US11635197
申请日：2006-12-07
申请人： Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
发明人： Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
IPC分类号： H04L27/08
CPC分类号： H04L27/0002 , H03G3/001 , H03G3/3068
摘要： Provided is an apparatus for automatic gain control (AGC) widely used in a receiver of a wireless communication system. The receiver of a wireless communication system includes: a step variable gain amplifier and an analog variable gain amplifier disposed in the path of a wireless signal and amplifying the wireless signal; an analog gain control unit for generating a gain control voltage for feedback-controlling an amplification value of the analog variable gain amplifier; a digital gain control unit for receiving the control voltage and generating a digital code determining an amplification value of the step variable gain amplifier. The apparatus for AGC constituted as described above can reduce power consumption and the number of devices by efficiently running an AGC loop in an analog domain, and can be embodied at low cost in a structure appropriately controlling the step gain amplifier and the analog gain amplifier.
摘要翻译：提供了广泛用于无线通信系统的接收机中的自动增益控制（AGC）的装置。无线通信系统的接收机包括：设置在无线信号的路径中的步进可变增益放大器和模拟可变增益放大器，并放大无线信号; 模拟增益控制单元，用于产生用于反馈控制模拟可变增益放大器的放大值的增益控制电压; 数字增益控制单元，用于接收控制电压并产生确定阶跃可变增益放大器的放大值的数字代码。如上所述构成的AGC装置可以通过有效地运行模拟域中的AGC环路来降低功耗和装置数量，并且可以在适当地控制步进增益放大器和模拟增益放大器的结构中以低成本实现。

13. 发明申请

US20110084865A1 DIGITAL RF CONVERTER AND RF CONVERTING METHOD THEREOF 有权
标题翻译：数字射频转换器及其RF转换方法
公开(公告)号：US20110084865A1
公开(公告)日：2011-04-14
申请号：US12902125
申请日：2010-10-11
申请人： Jang Hong CHOI , Hyun Ho Boo , Hyun Kyu Yu
发明人： Jang Hong CHOI , Hyun Ho Boo , Hyun Kyu Yu
IPC分类号： H03M1/66
CPC分类号： H03M3/504 , H03M3/32
摘要： Provided are a digital radio frequency (RF) converter and an RF converting method thereof. The RF frequency converter includes first and second RF output terminals of a differential form outputting an RF signal; a differential switch selectively connecting first and second nodes into the first and second RF output terminals in response to an oscillating waveform; at least one digital delay device column outputting a plurality of unit bits by sequentially delaying an input bit corresponding to the digital input signal; a front-end processor summing an output of the at least one digital delay device column; a plurality of current sources; and a plurality of first switches corresponding to the plurality of current sources, respectively, and delivering currents of current sources whose number corresponds to the sum value of the front-end processor among the plurality of current sources, to one of the first and second nodes.
摘要翻译：提供一种数字射频（RF）转换器及其RF转换方法。 RF频率转换器包括输出RF信号的差分形式的第一和第二RF输出端; 差分开关响应于振荡波形选择性地将第一和第二节点连接到第一和第二RF输出端子中; 至少一个数字延迟装置列通过顺序地延迟对应于数字输入信号的输入位而输出多个单位位; 前端处理器对所述至少一个数字延迟装置列的输出求和; 多个电流源; 以及分别对应于多个电流源的多个第一开关，并将数量对应于多个电流源中的前端处理器的和值的电流源的电流传送到第一和第二节点之一。

14. 发明授权

US07911248B2 Apparatus for linearization of digitally controlled oscillator 有权
标题翻译：数字控制振荡器线性化装置
公开(公告)号：US07911248B2
公开(公告)日：2011-03-22
申请号：US12629701
申请日：2009-12-02
申请人： Jang Hong Choi , Hyun Kyu Yu
发明人： Jang Hong Choi , Hyun Kyu Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/0991 , H03L7/093
摘要： There is provided an apparatus for the linearization of a digitally controlled oscillator. The apparatus includes a first filter outputting only a low frequency band signal of an input signal to the digitally controlled oscillator; a negative feedback loop causing the signal of an input port of the digitally controlled oscillator to pass through a frequency table and a frequency-to-digital code mapper in sequence and correcting an input of the digitally controlled oscillator by performing negative feedback to an input port of the first filter; and a frequency table generator storing a frequency value of an output signal of the digitally controlled oscillator in the frequency table.
摘要翻译：提供了一种用于数字控制振荡器的线性化的装置。该装置包括仅将输入信号的低频信号输出到数控振荡器的第一滤波器; 使得数字控制振荡器的输入端口的信号顺序通过频率表和频数码复用器的负反馈环路，并通过对输入端口执行负反馈来校正数字控制振荡器的输入的第一个过滤器; 以及频率表生成器，其存储频率表中数字控制振荡器的输出信号的频率值。

15. 发明授权

US07759703B2 Photo-detector array device with ROIC monolithically integrated for laser-radar image signal and manufacturing method thereof 失效
标题翻译：用于激光雷达图像信号的ROIC单片集成的光电检测器阵列器件及其制造方法
公开(公告)号：US07759703B2
公开(公告)日：2010-07-20
申请号：US12143584
申请日：2008-06-20
申请人： Eun Soo Nam , Myoung Sook Oh , Ho Young Kim , Young Jun Chong , Hyun Kyu Yu
发明人： Eun Soo Nam , Myoung Sook Oh , Ho Young Kim , Young Jun Chong , Hyun Kyu Yu
IPC分类号： H01L29/737
CPC分类号： H01L27/14643 , G01S7/4863 , G01S17/89 , H01L27/14681 , H04N5/369
摘要： A photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal and a manufacturing method thereof are provided. According to the photo-detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate, so that it is possible to simplify manufacturing processes and to greatly increasing yield. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically speared from each other by using a polyimide. Therefore, a PN junction surface of the photodiode is buried, so that a surface leakage current can be reduced and an electrical reliability can be improved. In addition, a structure of the control devices can be simplified, so that image signal reception characteristics can be improved.
摘要翻译：提供了与用于激光雷达图像信号单片集成的读出集成电路（ROIC）集成的光电检测器阵列装置及其制造方法。根据光检测器阵列器件，在InP衬底上同时形成用于选择和输出激光雷达图像信号的光电二极管和控制装置，从而可以简化制造工艺并大大提高产量。此外，在InP衬底上同时形成光电二极管和控制装置之后，通过使用聚酰亚胺将光电二极管和控制装置电分离。因此，埋入光电二极管的PN结表面，从而能够减小表面泄漏电流，提高电气可靠性。此外，可以简化控制装置的结构，从而可以提高图像信号接收特性。

16. 发明申请

US20100134335A1 APPARATUS FOR COMPENSATING FOR ERROR OF TIME-TO-DIGITAL CONVERTER 有权
标题翻译：用于补偿时间到数字转换器错误的装置
公开(公告)号：US20100134335A1
公开(公告)日：2010-06-03
申请号：US12629020
申请日：2009-12-01
申请人： Mi Jeong Park , Byung Hun Min , Ja Yol Lee , Hyun Kyu Yu
发明人： Mi Jeong Park , Byung Hun Min , Ja Yol Lee , Hyun Kyu Yu
IPC分类号： H03M1/06
CPC分类号： G04F10/06 , H03L7/085 , H03L2207/50
摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.
摘要翻译：公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间分辨率提高N倍（N是自然数）。该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一到第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

17. 发明申请

US20090146724A1 SWITCHING CIRCUIT FOR MILLIMETER WAVEBAND CONTROL CIRCUIT 有权
标题翻译：用于微波波形控制电路的切换电路
公开(公告)号：US20090146724A1
公开(公告)日：2009-06-11
申请号：US12139046
申请日：2008-06-13
申请人： Jae Kyoung Mun , Dong Young Kim , Jong Won Lim , Ho Kyun Ahn , Hae Cheon Kim , Hyun Kyu Yu
发明人： Jae Kyoung Mun , Dong Young Kim , Jong Won Lim , Ho Kyun Ahn , Hae Cheon Kim , Hyun Kyu Yu
IPC分类号： H03K17/06
CPC分类号： H03K17/063 , H01P1/15 , H03K17/693 , H03K2017/066
摘要： Provided is a switching circuit for a millimeter waveband control circuit. The switching circuit for a millimeter waveband control circuit includes a switching cell disposed on a signal port path to match an interested frequency and including at least one transistor coupled vertically to an input/output transmission line and a plurality of ground via holes disposed symmetrically in an upper portion and a lower portion of the input/output transmission line; capacitors for stabilizing a bias of the switching cell; and bias pads coupled in parallel to the capacitor to control the switching cell. Therefore, the switching circuit may be useful to improve its isolation by simplifying its design and layout through the use of symmetrical structure of optimized switching cells without the separate use of different switch elements, and also to reduce its manufacturing cost through the improved yield of the manufacturing process and the enhanced integration since it is possible to reduce a chip size of an integrated circuit in addition to its low insertion loss.
摘要翻译：提供了一种用于毫米波段控制电路的开关电路。毫米波段控制电路的开关电路包括设置在信号端口路径上以匹配感兴趣频率并且包括垂直于输入/输出传输线耦合的至少一个晶体管的开关单元和对称地布置在其中的多个接地通孔输入/输出传输线的上部和下部; 用于稳定开关电池的偏置的电容器; 以及与电容器并联耦合的偏置焊盘以控制开关单元。因此，切换电路可能有助于通过简化其设计和布局来改善其隔离，通过使用优化的开关电池的对称结构，而不需要分开使用不同的开关元件，并且还可以通过提高产量来提高其制造成本制造工艺和增强的集成，因为除了低插入损耗之外，可以减小集成电路的芯片尺寸。

18. 发明申请

US20090146197A1 PHOTO-DETECTOR ARRAY DEVICE WITH ROIC MONOLITHICALLY INTEGRATED FOR LASER-RADAR IMAGE SIGNAL AND MANUFACTURING METHOD THEREOF 失效
标题翻译：具有单色集成的激光雷达图像信号的光电检测器阵列器件及其制造方法
公开(公告)号：US20090146197A1
公开(公告)日：2009-06-11
申请号：US12143584
申请日：2008-06-20
申请人： Eun Soo Nam , Myoung Sook Oh , Ho Young Kim , Young Jun Chong , Hyun Kyu Yu
发明人： Eun Soo Nam , Myoung Sook Oh , Ho Young Kim , Young Jun Chong , Hyun Kyu Yu
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L27/14643 , G01S7/4863 , G01S17/89 , H01L27/14681 , H04N5/369
摘要： A photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal and a manufacturing method thereof are provided. According to the photo-detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate, so that it is possible to simplify manufacturing processes and to greatly increasing yield. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically speared from each other by using a polyimide. Therefore, a PN junction surface of the photodiode is buried, so that a surface leakage current can be reduced and an electrical reliability can be improved. In addition, a structure of the control devices can be simplified, so that image signal reception characteristics can be improved.
摘要翻译：提供了与用于激光雷达图像信号单片集成的读出集成电路（ROIC）集成的光电检测器阵列装置及其制造方法。根据光检测器阵列器件，在InP衬底上同时形成用于选择和输出激光雷达图像信号的光电二极管和控制装置，从而可以简化制造工艺并大大提高产量。此外，在InP衬底上同时形成光电二极管和控制装置之后，通过使用聚酰亚胺将光电二极管和控制装置电分离。因此，埋入光电二极管的PN结表面，从而能够减小表面泄漏电流，提高电气可靠性。此外，可以简化控制装置的结构，从而可以提高图像信号接收特性。

19. 发明申请

US20090134944A1 CAPACITIVE-DEGENERATION DOUBLE CROSS-COUPLED VOLTAGE-CONTROLLED OSCILLATOR 有权
标题翻译：电容式变压器双相交流电压控制振荡器
公开(公告)号：US20090134944A1
公开(公告)日：2009-05-28
申请号：US12114705
申请日：2008-05-02
申请人： Ja Yol Lee , Sang Heung Lee , Hae Cheon Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Sang Heung Lee , Hae Cheon Kim , Hyun Kyu Yu
IPC分类号： H03B5/12
CPC分类号： H03B5/1231 , H03B5/1212 , H03B5/1215 , H03B5/1221 , H03B5/1253
摘要： A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.
摘要翻译：提供电容变性双交叉耦合压控振荡器。电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容以增加主交叉振荡单元的负电阻。因此，可以增加最大可获得的振荡频率并降低输入电容。

20. 发明授权

US07456063B2 Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method 有权
标题翻译：半导体集成电路电源线布局方法和半导体集成电路布局方法
公开(公告)号：US07456063B2
公开(公告)日：2008-11-25
申请号：US11523212
申请日：2006-09-19
申请人： Sang Jin Byun , Hyun Kyu Yu
发明人： Sang Jin Byun , Hyun Kyu Yu
IPC分类号： H01L21/8242
CPC分类号： H01L27/0207
摘要： Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.
摘要翻译：提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化可以防止到去耦电容器的电源线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式