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11. 发明授权

US06961403B1 Programmable frequency divider with symmetrical output 有权
标题翻译：具有对称输出的可编程分频器
公开(公告)号：US06961403B1
公开(公告)日：2005-11-01
申请号：US10709804
申请日：2004-05-28
申请人： John S. Austin , Matthew T. Sobel
发明人： John S. Austin , Matthew T. Sobel
IPC分类号： H03K23/64 , G11C19/00 , H03B19/00
CPC分类号： G11C19/00
摘要： A programmable frequency divider circuit with symmetrical output is disclosed. The frequency divider includes a non-symmetrical LFSR based component operated in series with a symmetrical divider component. Both the LFSR and the symmetrical divider may be programmed to provide flexibility. The frequency divider can dynamically adjust the divisor of the LFSR component to overcome limitations in the divide resolution due to the series combination of dividers, providing even and odd divisor values. The divider architecture can also provide higher level functions, including synchronization of multiple divider outputs, dynamic switching of divisor values and generation of multi-phased and spaced outputs. The linear feedback shift register (LFSR) component includes a feedback logic network decomposed into multiple stages to realize a maximum latch-to-latch operational latency of one gate delay regardless of the size of the LFSR.
摘要翻译：公开了一种具有对称输出的可编程分频器电路。分频器包括与对称分频器组件串联操作的基于非对称LFSR的组件。可以对LFSR和对称分频器进行编程以提供灵活性。分频器可以动态调整LFSR分量的除数，以克服由于分频器的串联组合造成的分频分辨率的限制，从而提供均匀和除数。分频器架构还可以提供更高级别的功能，包括多个分频器输出的同步，除数值的动态切换以及多相和间隔输出的产生。线性反馈移位寄存器（LFSR）组件包括分解成多级的反馈逻辑网络，以实现一个门延迟的最大锁存到锁存操作等待时间，而不管LFSR的大小。

12. 发明授权

US08791728B2 High frequency CMOS programmable divider with large divide ratio 有权
标题翻译：具有大分频比的高频CMOS可编程分频器
公开(公告)号：US08791728B2
公开(公告)日：2014-07-29
申请号：US13275369
申请日：2011-10-18
申请人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
发明人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
IPC分类号： H03K21/00
CPC分类号： H03K19/1737 , H03K19/17744
摘要： A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs.
摘要翻译：动态锁存器具有一对并行通道门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。附加的通过门可操作地连接到第一锁存逻辑电路。一个附加的传递门控制更新的数据信号的通过。反相器从传递门接收更新的数据信号，并将更新的数据信号反相并输出为输出数据信号。因此，动态锁存器包括两对输入到该对并行通道门中，并且对接收到的数据信号仅执行四个逻辑运算中的一个。使用施加到两个输入的信号来执行四个逻辑运算。

13. 发明授权

US07088190B2 Voltage-controlled oscillators having controlling circuits 失效
标题翻译：具有控制电路的压控振荡器
公开(公告)号：US07088190B2
公开(公告)日：2006-08-08
申请号：US10709811
申请日：2004-05-28
申请人： John S. Austin , Melissa A. Beacom , Charles J. Masenas
发明人： John S. Austin , Melissa A. Beacom , Charles J. Masenas
IPC分类号： H03B5/24
CPC分类号： H03K3/012 , H03K3/0315
摘要： A voltage-controlled oscillator (VCO) comprising an odd number of delay stage circuits. Each delay stage circuit operates between supply voltages VDD and VSS (VDD>VSS) and comprises (1) an input node, (2) an output node, (3) an inverting circuit, and (4) an electric discharge path coupling the output node to VSS. The electric discharge path includes a switch circuit and a resistance adjusting circuit electrically coupled in series between the output node and VSS. In response to an input signal rising at the input node, the inverting circuit decreases an output signal at the output node, and the electric discharge path opens to help pull the output signal down faster. In response to an input signal falling at the input node, the inverting circuit increases the output signal at the output node, and the electric discharge path closes to minimize its own effect.
摘要翻译：包括奇数个延迟级电路的压控振荡器（VCO）。每个延迟级电路在电源电压VDD和VSS（VDD> VSS）之间工作，并且包括（1）输入节点，（2）输出节点，（3）反相电路，以及（4）将输出节点到VSS。放电路径包括在输出节点和VSS之间串联电耦合的开关电路和电阻调节电路。响应于在输入节点处上升的输入信号，反相电路减小输出节点处的输出信号，并且放电路径打开以帮助较快地拉出输出信号。响应于在输入节点处的输入信号，反相电路增加输出节点处的输出信号，并且放电路径关闭以最小化其自身的效果。

14. 发明授权

US4985975A System for attaching a fitting to a tube 失效
标题翻译：用于将配件连接到管的系统
公开(公告)号：US4985975A
公开(公告)日：1991-01-22
申请号：US456158
申请日：1989-12-22
申请人： John S. Austin , Jeff D. Gruenberg
发明人： John S. Austin , Jeff D. Gruenberg
IPC分类号： B21D39/04
CPC分类号： B21D39/04 , F16L13/147 , F16L23/024 , Y10T29/4994 , Y10T29/5367 , Y10T29/53996 , Y10T403/4933 , Y10T403/4941
摘要： The present invention includes a system and a method for attaching the end of a tube of a plastically deformable material such as titanium to a hard metal fitting in a manner that can provide the resulting tube joint with increased strength and fatigue resistance. In the method the tube and fitting are assembled by inserting the tube into the end of a bore in the fitting. A radial force is exerted against a predetermined axial length of the tube wall, and thus also against the fitting, to plastically deform the tube wall radially into plural, axially spaced, circumferential grooves in the fitting bore. While this radial force is being exerted, a die restrains the fitting, causing it to deform elastically more near the end of the fitting bore than near the end of the tube. In the resulting tube joint the fitting applies residual circumferential stresses to the tube that are larger near the end of the fitting bore, and this stress distribution increases the fatigue resistance of the tube joint.
摘要翻译：本发明包括一种系统和方法，用于将可塑性变形的材料如钛的管的端部以能够为所得到的管接头提供增强的强度和抗疲劳性的方式附着在硬金属配件上。在该方法中，通过将管插入配件中的孔的端部来组装管和接头。径向力被施加在管壁的预定轴向长度上，并且因此也抵靠配件，以使管壁塑性地变形成径向地嵌入配合孔中的多个轴向间隔开的周向槽。在施加该径向力的同时，模具限制配件，使得其在接近孔的端部附近弹性更靠近管的端部变形。在所得到的管接头中，配件在接近孔的端部附近对管施加残余圆周应力，并且该应力分布增加了管接头的抗疲劳性。

15. 发明授权

US08471595B1 Selectable dynamic/static latch with embedded logic 有权
标题翻译：具有嵌入式逻辑的可选动态/静态锁存器
公开(公告)号：US08471595B1
公开(公告)日：2013-06-25
申请号：US13353383
申请日：2012-01-19
申请人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin , Michael R. Ouellette
发明人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin , Michael R. Ouellette
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K3/35606 , G06F7/68 , H03K19/1737
摘要： A selectable latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. The output of the parallel pass gates and the additional pass gate is connected to a feedback loop. The feedback loop operates as a dynamic latch for high frequency applications or as a static latch for low frequency applications. Thus, the selectable latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal.
摘要翻译：可选择的锁存器具有一对并行通过门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。附加的通过门可操作地连接到第一锁存逻辑电路。一个附加的传递门控制更新的数据信号的通过。并联栅极和附加栅极的输出端连接到反馈回路。反馈回路作为高频应用的动态锁存器或作为低频应用的静态锁存器。因此，可选择的锁存器包括两个输入到该对并行通道门中，并且仅对接收的数据信号执行四个逻辑运算中的一个。

16. 发明申请

US20130093481A1 HIGH FREQUENCY CMOS PROGRAMMABLE DIVIDER WITH LARGE DIVIDE RATIO 失效
标题翻译：高频CMOS可编程分频器，具有大的分辨率
公开(公告)号：US20130093481A1
公开(公告)日：2013-04-18
申请号：US13275367
申请日：2011-10-18
申请人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
发明人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
IPC分类号： H03L7/08
CPC分类号： H03L7/183 , H03K23/54
摘要： A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal.
摘要翻译：锁相环（PLL）包括具有反馈分压器的PLL反馈电路。反馈分压器具有第一动态锁存器，第一逻辑电路和多个串联连接的动态锁存器。每个串行连接的动态锁存器将附加的数据信号接收并串行连接到后续串行的动态锁存器。该系列中的第二个到最后一个动态锁存器将第四个数据信号输出到该系列中的最后一个动态锁存器。最后的动态锁存器接收第四数据信号并输出第五数据信号。第一反馈回路从第二到最后动态锁存器接收第四数据信号，并从最后一个动态锁存器接收第五数据信号。第一反馈环路包括组合第四和第五数据信号的NAND电路，第一反馈环路输出第一反馈信号。

17. 发明授权

US06879654B2 Non-integer frequency divider circuit 失效
标题翻译：非整数分频电路
公开(公告)号：US06879654B2
公开(公告)日：2005-04-12
申请号：US10249629
申请日：2003-04-25
申请人： John S. Austin
发明人： John S. Austin
IPC分类号： H03K23/68 , H03K21/00
CPC分类号： H03K23/68
摘要： A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base stages to another such that only one of the base stages is enabled at any give time. The enable bit has a pulse width of one clock cycle. The outputs from the base stages are grouped together by an OR gate to generate a single output that is a fraction of an input clock signal.
摘要翻译：公开了一种非整数分频器。非整数分频器电路包括彼此连接的多个基级。非整数分频器电路还包括时钟电路，用于将使能位从一个基极级传递到另一个，使得在任何给定时间仅允许一个基极级被使能。使能位具有一个时钟周期的脉冲宽度。来自基极级的输出由或门组合在一起，以产生作为输入时钟信号的一小部分的单个输出。

18. 发明授权

US08525561B2 Phase lock loop having high frequency CMOS programmable divider with large divide ratio 失效
标题翻译：锁相环具有分频比大的高频CMOS可编程分频器
公开(公告)号：US08525561B2
公开(公告)日：2013-09-03
申请号：US13275367
申请日：2011-10-18
申请人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
发明人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
IPC分类号： H03K21/00
CPC分类号： H03L7/183 , H03K23/54
摘要： A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal.
摘要翻译：锁相环（PLL）包括具有反馈分压器的PLL反馈电路。反馈分压器具有第一动态锁存器，第一逻辑电路和多个串联连接的动态锁存器。每个串行连接的动态锁存器将附加的数据信号接收并串行连接到后续串行的动态锁存器。串联中的第二个到最后一个动态锁存器将第四个数据信号输出到该系列中的最后一个动态锁存器。最后的动态锁存器接收第四数据信号并输出第五数据信号。第一反馈回路从第二到最后动态锁存器接收第四数据信号，并从最后一个动态锁存器接收第五数据信号。第一反馈环路包括组合第四和第五数据信号的NAND电路，第一反馈环路输出第一反馈信号。

19. 发明申请

US20130093463A1 HIGH FREQUENCY CMOS PROGRAMMABLE DIVIDER WITH LARGE DIVIDE RATIO 有权
标题翻译：高频CMOS可编程分频器，具有大的分辨率
公开(公告)号：US20130093463A1
公开(公告)日：2013-04-18
申请号：US13275369
申请日：2011-10-18
申请人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
发明人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
IPC分类号： H03K19/173
CPC分类号： H03K19/1737 , H03K19/17744
摘要： A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs.
摘要翻译：动态锁存器具有一对并行通道门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。附加的通过门可操作地连接到第一锁存逻辑电路。一个附加的传递门控制更新的数据信号的通过。反相器从传递门接收更新的数据信号，并将更新的数据信号反相并输出为输出数据信号。因此，动态锁存器包括两对输入到该对并行通道门中，并且对接收到的数据信号仅执行四个逻辑运算中的一个。使用施加到两个输入的信号来执行四个逻辑运算。

20. 发明授权

US5546052A Phase locked loop circuit with phase/frequency detector which eliminates dead zones 失效
标题翻译：具有相位/频率检测器的锁相环电路，可消除死区
公开(公告)号：US5546052A
公开(公告)日：1996-08-13
申请号：US298639
申请日：1994-11-10
申请人： John S. Austin , Ilya I. Novof , Donald E. Strayer , Stephen D. Wyatt
发明人： John S. Austin , Ilya I. Novof , Donald E. Strayer , Stephen D. Wyatt
IPC分类号： H03D13/00 , H03K3/0231 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/10
CPC分类号： H03L7/095 , H03K3/0231 , H03L7/0893 , H03D13/004 , H03L2207/06 , H03L7/0896 , H03L7/0898 , Y10S331/02
摘要： A phase locked loop circuit is provided which includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which do not have "dead zones". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has a voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is also provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.
摘要翻译：提供了一种锁相环电路，其包括相位/频率检测器，其使用分频器电路和来自时钟分配树的反馈来产生不具有“死区”的INC和DEC脉冲。一对电荷泵接收INC和DEC脉冲。一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。通过该电荷泵将差分电流输出到环路滤波电容器。另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。还提供了抖动控制电路，其减少锁定相中的电流控制振荡器输出中的抖动。而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。

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