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11. 发明授权

US07856607B2 System and method for generating at-speed structural tests to improve process and environmental parameter space coverage 有权
标题翻译：用于生成高速结构测试以改进过程和环境参数空间覆盖的系统和方法
公开(公告)号：US07856607B2
公开(公告)日：2010-12-21
申请号：US11934146
申请日：2007-11-02
申请人： Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F11/24 , G01R31/31835
摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.
摘要翻译：一种提高高速结构测试（ASST）实用性的系统。在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。第三种方法是选择逻辑电路的节点作为关键性分析的函数。第四种装置根据所选节点的临界概率来选择定时路径。第五装置为每个所选定时路径生成ASST模式。提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

12. 发明申请

US20090119629A1 SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPROVE PROCESS AND ENVIRONMENTAL PARAMETER SPACE COVERAGE 有权
标题翻译：用于产生速度快速结构测试以改进过程和环境参数空间覆盖的系统和方法
公开(公告)号：US20090119629A1
公开(公告)日：2009-05-07
申请号：US11934146
申请日：2007-11-02
申请人： Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F11/24 , G01R31/31835
摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.
摘要翻译：一种提高高速结构测试（ASST）实用性的系统。在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。第三种方法是选择逻辑电路的节点作为关键性分析的函数。第四种装置根据所选节点的临界概率来选择定时路径。第五装置为每个所选定时路径生成ASST模式。提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

13. 发明授权

US09557378B2 Method and structure for multi-core chip product test and selective voltage binning disposition 有权
标题翻译：多核芯片产品测试和选择性电压组合配置的方法和结构
公开(公告)号：US09557378B2
公开(公告)日：2017-01-31
申请号：US13553986
申请日：2012-07-20
申请人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
发明人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
IPC分类号： H01L21/66 , G01R31/02 , G06F19/00 , G01R31/317 , G06F1/32
CPC分类号： G01R31/31718 , G01R31/31725 , G06F1/32
摘要： Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.
摘要翻译：测试集成电路器件的工作速度，以在最大和最小电压下建立最大和最小频率。将器件分类为相对较慢且相对较快的器件，以将器件分类到不同的电压仓。对于在系统使用条件下核心性能所需的每个电压箱，建立了一个特定于特定电压限制。特定于箱体的电压限制与系统最大和最小频率规格下的核心最小芯片级功能电压进行比较。该方法在设计最大和最小电压条件下将设计最大和最小频率的系统设计评估与测试的最大和最小电压条件下的最大和最小频率进行了评估。为器件建立芯片专用功能电压限制。来自电压仓的所有器件的初始系统电压设置在特定于器件的电压限制和芯片专用功能电压限制的更大值与评估条件一致。

14. 发明申请

US20140024145A1 METHOD AND STRUCTURE FOR MULTI-CORE CHIP PRODUCT TEST AND SELECTIVE VOLTAGE BINNING DISPOSITION 有权
标题翻译：多核芯片产品测试和选择性电压调整处理方法与结构
公开(公告)号：US20140024145A1
公开(公告)日：2014-01-23
申请号：US13553986
申请日：2012-07-20
申请人： JEANNE P. BICKFORD , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
发明人： JEANNE P. BICKFORD , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
IPC分类号： H01L21/66 , G01R31/02 , G06F19/00
CPC分类号： G01R31/31718 , G01R31/31725 , G06F1/32
摘要： Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.
摘要翻译：测试集成电路器件的工作速度，以在最大和最小电压下建立最大和最小频率。将器件分类为相对较慢且相对较快的器件，以将器件分类到不同的电压仓。对于在系统使用条件下核心性能所需的每个电压箱，建立了一个特定于特定电压限制。特定于箱体的电压限制与系统最大和最小频率规格下的核心最小芯片级功能电压进行比较。该方法在设计最大和最小电压条件下将设计最大和最小频率的系统设计评估与测试的最大和最小电压条件下的最大和最小频率进行了评估。为器件建立芯片专用功能电压限制。来自电压仓的所有器件的初始系统电压设置在特定于器件的电压限制和芯片专用功能电压限制的更大值与评估条件一致。

15. 发明申请

US20110055650A1 Hold Transition Fault Model and Test Generation Method 有权
标题翻译：保持过渡故障模型和测试生成方法
公开(公告)号：US20110055650A1
公开(公告)日：2011-03-03
申请号：US12548977
申请日：2009-08-27
申请人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
发明人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
IPC分类号： G06F11/263 , G01R31/28
CPC分类号： G01R31/318357 , G01R31/318328
摘要： A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.
摘要翻译：一种保持故障建模和测试生成的方法。该方法包括首先建模多个电路网络的快速上升和快速降档保持故障。测试快速上升保持故障通过以下方式实现：将多个电路节点中的每一个上的逻辑值设置为0; 使用单个时钟脉冲将多个电路节点中的每一个从0转换到1; 以及确定至少一个下游节点是否被从0变为1的不期望的影响。通过以下方式来实现快速降档保持：通过在多个电路节点中的每一个上设置逻辑值到1; 使用单个时钟脉冲将多个电路节点中的每一个从1转换到0; 以及确定至少一个下游节点是否被从1到0的过渡中无意地影响。

16. 发明授权

US07721170B2 Apparatus and method for selectively implementing launch off scan capability in at speed testing 失效
标题翻译：用于在速度测试中选择性地实施发射扫描能力的装置和方法
公开(公告)号：US07721170B2
公开(公告)日：2010-05-18
申请号：US11874972
申请日：2007-10-19
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318541
摘要： An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.
摘要翻译：一种用于在集成电路装置的高速测试中选择性地实施发射扫描能力的装置包括控制装置，其被配置为选择性地禁用被测闩锁结构的主时钟信号，使得系统时钟信号的脉冲序列导致被锁存结构中的从主从主时钟脉冲序列; 其中所述控制装置利用所述系统时钟信号作为其输入，并以相对于扫描链定时无关的自复位方式操作。

17. 发明申请

US20090106608A1 APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN CAPABILITY IN AT SPEED TESTING 失效
标题翻译：在速度测试中选择实现启动扫描能力的装置和方法
公开(公告)号：US20090106608A1
公开(公告)日：2009-04-23
申请号：US11874972
申请日：2007-10-19
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318541
摘要： An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.
摘要翻译：一种用于在集成电路装置的高速测试中选择性地实施发射扫描能力的装置包括控制装置，其被配置为选择性地禁用被测闩锁结构的主时钟信号，使得系统时钟信号的脉冲序列导致被锁存结构中的从主从主时钟脉冲序列; 其中所述控制装置利用所述系统时钟信号作为其输入，并以相对于扫描链定时无关的自复位方式操作。

18. 发明申请

US20090265677A1 INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENERATOR (CWG), DESIGN STRUCTURE AND METHOD 有权
标题翻译：集成测试波形发生器（TWG）和客户波形发生器（CWG），设计结构和方法
公开(公告)号：US20090265677A1
公开(公告)日：2009-10-22
申请号：US12104461
申请日：2008-04-17
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
IPC分类号： H03K5/156 , G06F1/10 , G06F17/50
CPC分类号： G06F17/505 , G06F1/10 , G06F2217/62 , H03K5/156
摘要： Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations. The deskewer circuit can selectively gate an input clock signal with the waveform signals from either the external or internal waveform generator in order to generate the required output clock signal.
摘要翻译：公开了时钟发生电路的实施例，用于电路的设计结构和相关联的方法，其提供了偏移功能，并进一步为测试和功能操作提供精确的定时。具体地说，这些实施例结合了能够从外部波形发生器和内部波形发生器接收波形信号的偏移电路。外部波形发生器可以生成和提供一个用于功能操作的波形信号。内部波形发生器可以独特地配置控制逻辑和计数器逻辑，用于为内置自检（BIST）操作，宏测试操作，其他测试操作中的任何一个生成和提供一对波形信号到电路板电路或功能操作。该偏移电路可以使用来自外部或内部波形发生器的波形信号选择性地输入输入时钟信号，以便产生所需的输出时钟信号。

19. 发明授权

US08181135B2 Hold transition fault model and test generation method 有权
标题翻译：保持转换故障模型和测试生成方法
公开(公告)号：US08181135B2
公开(公告)日：2012-05-15
申请号：US12548977
申请日：2009-08-27
申请人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
发明人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
IPC分类号： G06F17/50
CPC分类号： G01R31/318357 , G01R31/318328
摘要： A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.
摘要翻译：一种保持故障建模和测试生成的方法。该方法包括首先建模多个电路网络的快速上升和快速降档保持故障。测试快速上升保持故障通过以下方式实现：将多个电路节点中的每一个上的逻辑值设置为0; 使用单个时钟脉冲将多个电路节点中的每一个从0转换到1; 以及确定至少一个下游节点是否被从0变为1的不期望的影响。通过以下方式来实现快速降档保持：通过在多个电路节点中的每一个上设置逻辑值到1; 使用单个时钟脉冲将多个电路节点中的每一个从1转换到0; 以及确定至少一个下游节点是否被从1到0的过渡中无意地影响。

20. 发明授权

US07996807B2 Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method 有权
标题翻译：集成测试波形发生器（TWG）和客户波形发生器（CWG），设计结构和方法
公开(公告)号：US07996807B2
公开(公告)日：2011-08-09
申请号：US12104461
申请日：2008-04-17
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F1/10 , G06F2217/62 , H03K5/156
摘要： Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations. The deskewer circuit can selectively gate an input clock signal with the waveform signals from either the external or internal waveform generator in order to generate the required output clock signal.
摘要翻译：公开了时钟发生电路的实施例，用于电路的设计结构和相关联的方法，其提供了偏移功能，并进一步为测试和功能操作提供精确的定时。具体地说，这些实施例结合了能够从外部波形发生器和内部波形发生器接收波形信号的偏移电路。外部波形发生器可以生成和提供一个用于功能操作的波形信号。内部波形发生器可以独特地配置控制逻辑和计数器逻辑，用于为内置自检（BIST）操作，宏测试操作，其他测试操作中的任何一个产生和提供一对波形信号到电路板电路或功能操作。该偏移电路可以使用来自外部或内部波形发生器的波形信号选择性地输入输入时钟信号，以便产生所需的输出时钟信号。

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