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11. 发明申请

US20100032684A1 ION IMPLANTATION FOR SUPPRESSION OF DEFECTS IN ANNEALED SiGe LAYERS 有权
标题翻译：用于抑制退火SiGe层中的缺陷的离子植入
公开(公告)号：US20100032684A1
公开(公告)日：2010-02-11
申请号：US12539248
申请日：2009-08-11
申请人： Stephen W. Bedell , Huajie Chen , Keith E. Fogel , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Stephen W. Bedell , Huajie Chen , Keith E. Fogel , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L29/267 , H01L29/161 , H01L29/165
CPC分类号： H01L21/26506 , H01L21/02381 , H01L21/02532 , H01L21/02694 , H01L21/2658
摘要： A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.
摘要翻译：公开了一种制造具有减小的平面缺陷密度的基本上松弛的SiGe合金层的方法。本发明的方法包括在含Si衬底的表面上形成应变的含Ge层; 在含锗层/含Si衬底界面处或下方注入离子，并加热以形成具有减小的平面缺陷密度的基本上松弛的SiGe合金层。还提供了具有具有减小的平面缺陷密度的SiGe层以及含有该SiGe层的异质结构的基本上松弛的绝缘体上硅衬底材料。

12. 发明申请

US20080233687A1 ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION 有权
标题翻译：通过外延界面有限扩散形成的超声结构
公开(公告)号：US20080233687A1
公开(公告)日：2008-09-25
申请号：US12132698
申请日：2008-06-04
申请人： Huajie Chen , Omer H. Dokumaci , Oleg G. Gluschenkov , Werner A. Rausch
发明人： Huajie Chen , Omer H. Dokumaci , Oleg G. Gluschenkov , Werner A. Rausch
IPC分类号： H01L21/336
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
摘要翻译：形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。更具体地，本发明增加了硅衬底的顶表面的氧含量。优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。这允许本发明在硅衬底的顶表面上外延生长硅层。此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

13. 发明申请

US20080090366A1 Hybrid SOI-Bulk Semiconductor Transistors 失效
标题翻译：混合SOI-体半导体晶体管
公开(公告)号：US20080090366A1
公开(公告)日：2008-04-17
申请号：US11870436
申请日：2007-10-11
申请人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

14. 发明申请

US20070262361A1 STRUCTURE AND METHOD FOR MANUFACTURING STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS 有权
标题翻译：用混合晶体取向和不同应力水平制造具有应力的硅直接绝缘体衬底的结构和方法
公开(公告)号：US20070262361A1
公开(公告)日：2007-11-15
申请号：US11830464
申请日：2007-07-30
申请人： Huilong Zhu , Bruce Doris , Huajie Chen , Patricia Mooney , Stephen Bedell
发明人： Huilong Zhu , Bruce Doris , Huajie Chen , Patricia Mooney , Stephen Bedell
IPC分类号： H01L27/092
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.
摘要翻译：本发明提供了具有多个结晶取向的应变Si直接绝缘体（SSDOI）基板及其形成方法。广义上，但是具体来说，本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层，所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向，并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

15. 发明授权

US07176481B2 In situ doped embedded sige extension and source/drain for enhanced PFET performance 有权
标题翻译：用于增强PFET性能的原位掺杂嵌入式扩展和源极/漏极
公开(公告)号：US07176481B2
公开(公告)日：2007-02-13
申请号：US10905598
申请日：2005-01-12
申请人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry K. Utomo , Werner A. Rausch
发明人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry K. Utomo , Werner A. Rausch
IPC分类号： H01L29/06
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.
摘要翻译：公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

16. 发明申请

US20060292779A1 STRUCTURE AND METHOD FOR MAKING STRAINED CHANNEL FIELD EFFECT TRANSISTOR USING SACRIFICIAL SPACER 有权
标题翻译：使用真空间隔件制作应变通道场效应晶体管的结构和方法
公开(公告)号：US20060292779A1
公开(公告)日：2006-12-28
申请号：US11463777
申请日：2006-08-10
申请人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
IPC分类号： H01L21/8234
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.
摘要翻译：提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个晶体半导体合金，其设置在栅叠层的相对侧上。每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离，第一间隔物，第二距离与第一距离不同。

17. 发明申请

US20060255330A1 EMBEDDED SILICON GERMANIUM USING A DOUBLE BURIED OXIDE SILICON-ON-INSULATOR WAFER 有权
标题翻译：嵌入式硅胶锗，使用双层氧化硅绝缘体
公开(公告)号：US20060255330A1
公开(公告)日：2006-11-16
申请号：US10908394
申请日：2005-05-10
申请人： Huajie Chen , Dureseti Chidambarrao , Dominic Schepis , Henry Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Dominic Schepis , Henry Utomo
IPC分类号： H01L27/12 , H01L29/06
CPC分类号： H01L29/7842 , H01L27/1203 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L29/78603 , H01L29/78618 , H01L29/78684
摘要： Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.
摘要翻译：公开了一种形成pFET的p型场效应晶体管（pFET）结构和方法。 pFET在源极/漏极区域中包括嵌入的硅锗以增加p沟道上的纵向应力，从而增强晶体管的性能。通过增加源极/漏极区域的深度，从而增加嵌入式硅锗的体积来实现增加的应力。通过使用双BOX SOI晶片来实现应力硅锗源极/漏极区域的更大的深度（例如高达100nm）。通过第一硅层和第一掩埋氧化物层蚀刻沟槽，然后从第二硅层外延生长受应力的硅锗。第二掩埋氧化物层隔离pFET。

18. 发明授权

US07026249B2 SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth 有权
标题翻译： SiGe晶格工程使用氧化，稀化和外延再生长的组合
公开(公告)号：US07026249B2
公开(公告)日：2006-04-11
申请号：US10448954
申请日：2003-05-30
申请人： Stephen W. Bedell , Huajie Chen , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L21/302
CPC分类号： H01L21/7624 , H01L21/02381 , H01L21/02532 , H01L21/02664 , Y10T428/12674
摘要： The present invention provides a method of fabricating a SiGe-on-insulator substrate in which lattice engineering is employed to decouple the interdependence between SiGe thickness, Ge fraction and strain relaxation. The method includes providing a SiGe-on-insulator substrate material comprising a SiGe alloy layer having a selected in-plane lattice parameter, a selected thickness parameter and a selected Ge content parameter, wherein the selected in-plane lattice parameter has a constant value and one or both of the other parameters, i.e., thickness or Ge content, have adjustable values; and adjusting one or both of the other parameters to final selected values, while maintaining the selected in-plane lattice parameter. The adjusting is achieved utilizing either a thinning process or a thermal dilution process depending on which parameters are fixed and which are adjustable.
摘要翻译：本发明提供了一种制造绝缘体上硅衬底的方法，其中使用晶格工程来去耦合SiGe厚度，Ge分数和应变松弛之间的相互依赖性。该方法包括提供一种绝缘体上硅衬底材料，其包括具有选定的面内晶格参数的SiGe合金层，选定的厚度参数和所选择的Ge含量参数，其中所选择的面内晶格参数具有恒定值，一个或两个其他参数，即厚度或Ge含量，具有可调整的值; 并且在保持所选择的平面内晶格参数的同时将其他参数中的一个或两个调整为最终选择的值。根据哪些参数是固定的，哪些是可调节的，利用稀化过程或热稀释过程实现调节。

19. 发明授权

US06972247B2 Method of fabricating strained Si SOI wafers 失效
标题翻译：制造应变Si SOI晶片的方法
公开(公告)号：US06972247B2
公开(公告)日：2005-12-06
申请号：US10728519
申请日：2003-12-05
申请人： Stephen W. Bedell , Guy M. Cohen , Huajie Chen
发明人： Stephen W. Bedell , Guy M. Cohen , Huajie Chen
IPC分类号： H01L21/20 , H01L21/324 , H01L21/762 , H01L21/425
CPC分类号： H01L21/324
摘要： A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate in which the strained semiconductor is a thin semiconductor layer having a thickness of less than 50 nm that is located directly atop an insulator layer of a preformed silicon-on-insulator substrate is provided. Wafer bonding is not employed in forming the SSOI substrate of the present invention.
摘要翻译：一种制造应变半导体绝缘体（SSOI）衬底的方法，其中应变半导体是厚度小于50nm的薄半导体层，其直接位于预成型的绝缘体上硅衬底上的绝缘体层的顶部被提供。在形成本发明的SSOI基板时不使用晶片接合。

20. 发明申请

US20050236668A1 STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI CMOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C 有权
标题翻译：用SiGe和/或Si：C的栅极应力工程制造散装硅和SOI CMOS器件中的分解自由应力通道的结构和方法
公开(公告)号：US20050236668A1
公开(公告)日：2005-10-27
申请号：US10709239
申请日：2004-04-23
申请人： Huilong Zhu , Bruce Doris , Huajie Chen
发明人： Huilong Zhu , Bruce Doris , Huajie Chen
IPC分类号： H01L21/20 , H01L21/28 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/49 , H01L29/78 , H01L31/0392
CPC分类号： H01L29/7845 , H01L21/28035 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/4925 , H01L29/66545 , H01L29/7842
摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.
摘要翻译：公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

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