专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050189589A1 HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS 有权
标题翻译：混合SOI / BULK半导体晶体管
公开(公告)号：US20050189589A1
公开(公告)日：2005-09-01
申请号：US10708378
申请日：2004-02-27
申请人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L27/01 , H01L29/06 , H01L29/10 , H01L29/786
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

2. 发明申请

US20080090366A1 Hybrid SOI-Bulk Semiconductor Transistors 失效
标题翻译：混合SOI-体半导体晶体管
公开(公告)号：US20080090366A1
公开(公告)日：2008-04-17
申请号：US11870436
申请日：2007-10-11
申请人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

3. 发明申请

US20050045947A1 THIN CHANNEL FET WITH RECESSED SOURCE/DRAINS AND EXTENSIONS 失效
标题翻译：具有残留源/漏极和扩展的薄沟道FET
公开(公告)号：US20050045947A1
公开(公告)日：2005-03-03
申请号：US10604907
申请日：2003-08-26
申请人： Huajie Chen , Bruce Doris , Philip Oldiges , Xinlin Wang , Huilong Zhu
发明人： Huajie Chen , Bruce Doris , Philip Oldiges , Xinlin Wang , Huilong Zhu
IPC分类号： H01L21/336 , H01L29/10 , H01L29/786 , H01L29/76 , H01L29/745 , H01L31/062
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/66772 , H01L29/78603 , H01L29/78618 , H01L29/78621 , H01L29/78684
摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. The devices have a thin channel, e.g., an ultra-thin (smaller than or equal to 10 nanometers (10 nm)) silicon on insulator (SOI) layer. Source/drain regions are located in recesses at either end of the thin channel and are substantially thicker (e.g., 30 nm) than the thin channel. Source/drain extensions and corresponding source/drain regions are self aligned to the FET gate and thin channel.
摘要翻译：包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。器件具有薄沟道，例如超薄（小于或等于10纳米（10nm））绝缘体上硅（SOI）层。源极/漏极区位于薄沟道的任一端的凹槽中，并且比薄沟道基本上更厚（例如，30nm）。源/漏扩展和相应的源极/漏极区域与FET栅极和薄沟道自对准。

4. 发明申请

US20070181930A1 Structure and method of making double-gated self-aligned finfet having gates of different lengths 有权
标题翻译：制作具有不同长度的门的双门控自对准finfet的结构和方法
公开(公告)号：US20070181930A1
公开(公告)日：2007-08-09
申请号：US10711182
申请日：2004-08-31
申请人： Huilong Zhu , Bruce Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip Oldiges
发明人： Huilong Zhu , Bruce Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip Oldiges
IPC分类号： H01L27/108
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.
摘要翻译：提供了门控半导体器件，其中主体具有在平行于衬底的主表面的横向方向上延伸的第一尺寸，以及在至少基本上垂直且至少基本垂直于主表面的方向上延伸的第二尺寸，所述主体具有与所述第一侧相对的第一侧和第二侧。门控半导体器件包括覆盖第一侧的第一栅极，并且在横向上具有第一栅极长度。门控半导体器件还包括覆盖第二侧的第二栅极，第二栅极在横向上具有不同于第一栅极长度的第二栅极长度，并且优选地短于第一栅极长度。在一个实施例中，第一栅极和第二栅极彼此电隔离。在另一个实施例中，第一栅极主要由多晶硅锗组成，第二栅极主要由多晶硅组成。

5. 发明申请

US20070170507A1 STRUCTURE AND METHOD FOR MANUFACTURING PLANAR STRAINED Si/SiGe SUBSTRATE WITH MULTIPLE ORIENTATIONS AND DIFFERENT STRESS LEVELS 审中-公开
标题翻译：用于制造具有多个方位和不同应力水平的平面应变Si / SiGe衬底的结构和方法
公开(公告)号：US20070170507A1
公开(公告)日：2007-07-26
申请号：US11693377
申请日：2007-03-29
申请人： Huilong Zhu , Bruce Doris , Philip Oldiges , Meikei Ieong , Min Yang , Huajie Chen
发明人： Huilong Zhu , Bruce Doris , Philip Oldiges , Meikei Ieong , Min Yang , Huajie Chen
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84 , H01L27/1207 , Y10S438/938
摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.
摘要翻译：本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

6. 发明申请

US20060172495A1 STRUCTURE AND METHOD FOR MANUFACTURING PLANAR STRAINED Si/SiGe SUBSTRATE WITH MULTIPLE ORIENTATIONS AND DIFFERENT STRESS LEVELS 失效
标题翻译：用于制造具有多个方位和不同应力水平的平面应变Si / SiGe衬底的结构和方法
公开(公告)号：US20060172495A1
公开(公告)日：2006-08-03
申请号：US10905978
申请日：2005-01-28
申请人： Huilong Zhu , Bruce Doris , Philip Oldiges , Meikel Ioeng , Min Yang , Huajie Chen
发明人： Huilong Zhu , Bruce Doris , Philip Oldiges , Meikel Ioeng , Min Yang , Huajie Chen
IPC分类号： H01L21/8234
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84 , H01L27/1207 , Y10S438/938
摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.
摘要翻译：本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

7. 发明申请

US20060043421A1 MULTI-GATE DEVICE WITH HIGH K DIELECTRIC FOR CHANNEL TOP SURFACE 有权
标题翻译：具有高K介质的通道顶表面的多栅极器件
公开(公告)号：US20060043421A1
公开(公告)日：2006-03-02
申请号：US10711200
申请日：2004-09-01
申请人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
发明人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
IPC分类号： H01L27/10
CPC分类号： H01L29/785 , H01L29/66795
摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.
摘要翻译：多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。保护层可以在蚀刻过程中保护高k电介质层。

8. 发明申请

US20080070366A1 MULTI-GATE DEVICE WITH HIGH K DIELECTRIC FOR CHANNEL TOP SURFACE 失效
标题翻译：具有高K介质的通道顶表面的多栅极器件
公开(公告)号：US20080070366A1
公开(公告)日：2008-03-20
申请号：US11928787
申请日：2007-10-30
申请人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
发明人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.
摘要翻译：多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。保护层可以在蚀刻过程中保护高k电介质层。

9. 发明申请

US20060125008A1 DUAL STRESSED SOI SUBSTRATES 有权
标题翻译：双应力SOI衬底
公开(公告)号：US20060125008A1
公开(公告)日：2006-06-15
申请号：US10905062
申请日：2004-12-14
申请人： Dureseti Chidambarrao , Bruce Doris , Oleg Gluschenkov , Omer Dokumaci , Huilong Zhu
发明人： Dureseti Chidambarrao , Bruce Doris , Oleg Gluschenkov , Omer Dokumaci , Huilong Zhu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

10. 发明申请

US20060060925A1 SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT SURFACE DIRECTIONS AND METHODS 有权
标题翻译：具有不同表面方向的活动区域的半导体器件结构和方法
公开(公告)号：US20060060925A1
公开(公告)日：2006-03-23
申请号：US10711416
申请日：2004-09-17
申请人： Bruce Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
发明人： Bruce Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/045 , H01L21/76275 , H01L21/76278 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7842
摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.
摘要翻译：公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个其他。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式