专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08362575B2 Controlling the shape of source/drain regions in FinFETs 有权
公开(公告)号：US08362575B2
公开(公告)日：2013-01-29
申请号：US12831925
申请日：2010-07-07
申请人： Tsz-Mei Kwok , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Hsien-Hsin Lin
发明人： Tsz-Mei Kwok , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Hsien-Hsin Lin
IPC分类号： H01L27/088 , H01L21/70 , H01L21/02 , H01L29/06 , H01L29/04 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/7851 , H01L21/76 , H01L29/045 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

12. 发明申请

US20110210404A1 Epitaxy Profile Engineering for FinFETs 有权
标题翻译： FinFET的外延轮廓工程
公开(公告)号：US20110210404A1
公开(公告)日：2011-09-01
申请号：US12713573
申请日：2010-02-26
申请人： Chien-Chang Su , Tsz-Mei Kwok , Hsien-Hsin Lin , Hsueh-Chang Sung , Yi-Fang Pai , Kuan-Yu Chen
发明人： Chien-Chang Su , Tsz-Mei Kwok , Hsien-Hsin Lin , Hsueh-Chang Sung , Yi-Fang Pai , Kuan-Yu Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/02532 , H01L21/02636 , H01L21/823431 , H01L21/823821 , H01L29/785
摘要： A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
摘要翻译：一种形成集成电路结构的方法包括在衬底的主表面上提供包括衬底和半导体鳍片的晶片，并且执行沉积步骤以在半导体鳍片的顶表面和侧壁上外延生长外延层，其中外延层包括半导体材料。然后执行蚀刻步骤以去除外延层的一部分，其中外延层的剩余部分保留在半导体鳍片的顶表面和侧壁上。

13. 发明申请

US20110108894A1 METHOD OF FORMING STRAINED STRUCTURES IN SEMICONDUCTOR DEVICES 有权
标题翻译：在半导体器件中形成应变结构的方法
公开(公告)号：US20110108894A1
公开(公告)日：2011-05-12
申请号：US12613714
申请日：2009-11-06
申请人： Hsueh-Chang Sung , Hsien-Hsin Lin , Kuan-Yu Chen , Chien-Chang Su , Tsz-Mei Kwok , Yi-Fang Pai
发明人： Hsueh-Chang Sung , Hsien-Hsin Lin , Kuan-Yu Chen , Chien-Chang Su , Tsz-Mei Kwok , Yi-Fang Pai
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/7834
摘要： The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material.
摘要翻译：本公开提供了一种制造方法，包括提供半导体衬底; 在基板上形成栅极结构; 执行注入工艺以在所述衬底中形成掺杂区域; 在所述栅极结构的侧壁上形成间隔物; 执行第一蚀刻以在所述衬底中形成凹部，其中所述第一蚀刻去除所述掺杂区域的一部分; 执行第二蚀刻以扩大基板中的凹部，其中第二蚀刻包括蚀刻剂和提高在掺杂区域的剩余部分处的蚀刻速率的催化剂; 并用半导体材料填充凹部。

14. 发明授权

US09117905B2 Method for incorporating impurity element in EPI silicon process 有权
标题翻译：在EPI硅工艺中掺入杂质元素的方法
公开(公告)号：US09117905B2
公开(公告)日：2015-08-25
申请号：US12644869
申请日：2009-12-22
申请人： Chien-Chang Su , Hsien-Hsin Lin , Tsz-Mei Kwok , Kuan-Yu Chen , Hsueh-Chang Sung , Yi-Fang Pai
发明人： Chien-Chang Su , Hsien-Hsin Lin , Tsz-Mei Kwok , Kuan-Yu Chen , Hsueh-Chang Sung , Yi-Fang Pai
IPC分类号： H01L21/336 , H01L29/78 , H01L21/02 , H01L29/66
CPC分类号： H01L29/7851 , H01L21/02532 , H01L21/02573 , H01L21/02576 , H01L21/0262 , H01L29/0653 , H01L29/167 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括形成多个翅片，翅片通过隔离结构彼此隔离，在每个翅片的一部分上形成栅极结构; 在栅极结构的侧壁上分别形成间隔物，蚀刻每个鳍片的剩余部分，从而形成凹槽，外延生长硅以填充凹槽，包括掺杂选自锗（Ge），铟（In），和碳（C），并用n型掺杂剂掺杂硅epi。

15. 发明申请

US20110193141A1 METHOD OF FABRICATING A FINFET DEVICE 有权
标题翻译：制造FINFET器件的方法
公开(公告)号：US20110193141A1
公开(公告)日：2011-08-11
申请号：US12703918
申请日：2010-02-11
申请人： Hsien-Hsin Lin , Tsz-Mei Kwok , Chien-Chang Su
发明人： Hsien-Hsin Lin , Tsz-Mei Kwok , Chien-Chang Su
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/045 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate of a crystalline semiconductor material having a top surface of a first crystal plane orientation; a fin structure of the crystalline semiconductor material overlying the substrate; a gate structure over a portion of the fin structure; an epitaxy layer over another portion of the fin structure, the epitaxy layer having a surface having a second crystal plane orientation, wherein the epitaxy layer and underlying fin structure include a source and drain region, the source region being separated from the drain region by the gate structure; and a channel defined in the fin structure from the source region to the drain region, and aligned in a direction parallel to both the surface of the epitaxy layer and the top surface of the substrate.
摘要翻译：公开了一种用于制造FinFET器件的FinFET器件和方法。示例性的FinFET器件包括具有第一晶面取向的顶表面的晶体半导体材料的衬底; 覆盖衬底的晶体半导体材料的鳍状结构; 翅片结构的一部分上的栅极结构; 在鳍结构的另一部分上的外延层，所述外延层具有具有第二晶面取向的表面，其中所述外延层和下面的鳍结构包括源极和漏极区，源极区与漏极区分离，门结构; 以及在鳍结构中从源极区域到漏极区域限定的沟道，并且在平行于外延层的表面和衬底的顶表面的方向上排列。

16. 发明申请

US20120299121A1 Source/Drain Formation and Structure 有权
标题翻译：源/排水形成与结构
公开(公告)号：US20120299121A1
公开(公告)日：2012-11-29
申请号：US13114910
申请日：2011-05-24
申请人： Chii-Ming Wu , Chien-Chang Su , Hsien-Hsin Lin , Yi-Fang Pai
发明人： Chii-Ming Wu , Chien-Chang Su , Hsien-Hsin Lin , Yi-Fang Pai
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7834 , H01L21/2257 , H01L29/6659 , H01L29/66628 , H01L29/66636
摘要： A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.
摘要翻译：公开了一种用于形成半导体结构的系统和方法。一个实施例包括形成与栅极堆叠相邻的高扩散层，并形成与高扩散层相邻的低扩散性层。在形成这两层之后，进行退火以从栅叠层下方的高扩散层扩散掺杂剂以帮助形成沟道区。

17. 发明授权

US09537004B2 Source/drain formation and structure 有权
标题翻译：来源/排水沟形成和结构
公开(公告)号：US09537004B2
公开(公告)日：2017-01-03
申请号：US13114910
申请日：2011-05-24
申请人： Chii-Ming Wu , Chien-Chang Su , Hsien-Hsin Lin , Yi-Fang Pai
发明人： Chii-Ming Wu , Chien-Chang Su , Hsien-Hsin Lin , Yi-Fang Pai
IPC分类号： H01L29/78 , H01L21/336 , H01L21/225 , H01L29/66
CPC分类号： H01L29/7834 , H01L21/2257 , H01L29/6659 , H01L29/66628 , H01L29/66636
摘要： A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.
摘要翻译：公开了一种用于形成半导体结构的系统和方法。一个实施例包括形成与栅极堆叠相邻的高扩散层，并形成与高扩散层相邻的低扩散性层。在形成这两层之后，进行退火以从栅叠层下方的高扩散层扩散掺杂剂以帮助形成沟道区。

18. 发明授权

US08310013B2 Method of fabricating a FinFET device 有权
标题翻译：制造FinFET器件的方法
公开(公告)号：US08310013B2
公开(公告)日：2012-11-13
申请号：US12703918
申请日：2010-02-11
申请人： Hsien-Hsin Lin , Tsz-Mei Kwok , Chien-Chang Su
发明人： Hsien-Hsin Lin , Tsz-Mei Kwok , Chien-Chang Su
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/045 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate of a crystalline semiconductor material having a top surface of a first crystal plane orientation; a fin structure of the crystalline semiconductor material overlying the substrate; a gate structure over a portion of the fin structure; an epitaxy layer over another portion of the fin structure, the epitaxy layer having a surface having a second crystal plane orientation, wherein the epitaxy layer and underlying fin structure include a source and drain region, the source region being separated from the drain region by the gate structure; and a channel defined in the fin structure from the source region to the drain region, and aligned in a direction parallel to both the surface of the epitaxy layer and the top surface of the substrate.
摘要翻译：公开了一种用于制造FinFET器件的FinFET器件和方法。示例性的FinFET器件包括具有第一晶面取向的顶表面的晶体半导体材料的衬底; 覆盖衬底的晶体半导体材料的鳍状结构; 翅片结构的一部分上的栅极结构; 在鳍结构的另一部分上的外延层，所述外延层具有具有第二晶面取向的表面，其中所述外延层和下面的鳍结构包括源极和漏极区，源极区与漏极区分离由门结构; 以及在鳍结构中从源极区域到漏极区域限定的沟道，并且在平行于外延层的表面和衬底的顶表面的方向上排列。

19. 发明授权

US08884341B2 Integrated circuits 有权
标题翻译：集成电路
公开(公告)号：US08884341B2
公开(公告)日：2014-11-11
申请号：US13210962
申请日：2011-08-16
申请人： Chun Hsiung Tsai , Su-Hao Liu , Chien-Tai Chan , King-Yuen Wong , Chien-Chang Su
发明人： Chun Hsiung Tsai , Su-Hao Liu , Chien-Tai Chan , King-Yuen Wong , Chien-Chang Su
IPC分类号： H01L29/76 , H01L29/78 , H01L29/10 , H01L29/66 , H01L21/265 , H01L29/08
CPC分类号： H01L29/7834 , H01L21/26506 , H01L21/26586 , H01L29/0847 , H01L29/1083 , H01L29/66492 , H01L29/6653 , H01L29/66636
摘要： An integrated circuit includes a gate electrode disposed over a substrate. A source/drain (S/D) region is disposed adjacent to the gate electrode. The S/D region includes a diffusion barrier structure disposed in a recess of the substrate. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode. The second portion is distant from the gate electrode. An N-type doped silicon-containing structure is disposed over the diffusion barrier structure. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate. The second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.
摘要翻译：集成电路包括设置在基板上的栅电极。源极/漏极（S / D）区域邻近栅电极设置。 S / D区域包括设置在基板的凹部中的扩散阻挡结构。扩散阻挡结构包括第一部分和第二部分。第一部分与栅电极相邻。第二部分远离栅电极。在扩散阻挡结构上设置N型掺杂的含硅结构。扩散阻挡结构的第一部分被配置为部分地防止N型掺杂的含硅结构的N型掺杂剂扩散到衬底中。扩散阻挡结构的第二部分被配置为基本上完全防止N型掺杂含硅结构的N型掺杂剂扩散到衬底中。

20. 发明授权

US08557692B2 FinFET LDD and source drain implant technique 有权
标题翻译： FinFET LDD和源极漏极注入技术
公开(公告)号：US08557692B2
公开(公告)日：2013-10-15
申请号：US12686246
申请日：2010-01-12
申请人： Chun Hsiung Tsai , Chien-Chang Su , Tsung-Hung Li , Da-Wen Lin , Wen-Sheh Huang
发明人： Chun Hsiung Tsai , Chien-Chang Su , Tsung-Hung Li , Da-Wen Lin , Wen-Sheh Huang
IPC分类号： H01L21/40 , H01L21/02
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/823821 , H01L29/66795 , H01L29/66803
摘要： A method of forming an integrated circuit includes providing a semiconductor wafer; and forming a fin field-effect transistor (FinFET) including implanting the semiconductor wafer using a hot-implantation to form an implanted region in the FinFET. The implanted region comprises a region selected from the group consisting essentially of a lightly doped source and drain region, a pocket region, and a deep source drain region.
摘要翻译：一种形成集成电路的方法包括：提供半导体晶片; 以及形成鳍状场效应晶体管（FinFET），其包括使用热注入植入所述半导体晶片以在所述FinFET中形成注入区域。注入区域包括从基本上由轻掺杂的源极和漏极区域，口袋区域和深源极漏极区域组成的组中选择的区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式