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1. 发明授权

US08557692B2 FinFET LDD and source drain implant technique 有权
标题翻译： FinFET LDD和源极漏极注入技术
公开(公告)号：US08557692B2
公开(公告)日：2013-10-15
申请号：US12686246
申请日：2010-01-12
申请人： Chun Hsiung Tsai , Chien-Chang Su , Tsung-Hung Li , Da-Wen Lin , Wen-Sheh Huang
发明人： Chun Hsiung Tsai , Chien-Chang Su , Tsung-Hung Li , Da-Wen Lin , Wen-Sheh Huang
IPC分类号： H01L21/40 , H01L21/02
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/823821 , H01L29/66795 , H01L29/66803
摘要： A method of forming an integrated circuit includes providing a semiconductor wafer; and forming a fin field-effect transistor (FinFET) including implanting the semiconductor wafer using a hot-implantation to form an implanted region in the FinFET. The implanted region comprises a region selected from the group consisting essentially of a lightly doped source and drain region, a pocket region, and a deep source drain region.
摘要翻译：一种形成集成电路的方法包括：提供半导体晶片; 以及形成鳍状场效应晶体管（FinFET），其包括使用热注入植入所述半导体晶片以在所述FinFET中形成注入区域。注入区域包括从基本上由轻掺杂的源极和漏极区域，口袋区域和深源极漏极区域组成的组中选择的区域。

2. 发明申请

US20120070953A1 METHOD OF FORMING INTEGRATED CIRCUITS 有权
标题翻译：形成集成电路的方法
公开(公告)号：US20120070953A1
公开(公告)日：2012-03-22
申请号：US12886713
申请日：2010-09-21
申请人： De-Wei YU , Chun Hsiung TSAI , Yu-Lien HUANG , Chien-Tai CHAN , Wen-Sheh HUANG
发明人： De-Wei YU , Chun Hsiung TSAI , Yu-Lien HUANG , Chien-Tai CHAN , Wen-Sheh HUANG
IPC分类号： H01L21/336
CPC分类号： H01L29/66803 , H01L21/2236 , H01L21/2253 , H01L29/7848
摘要： A method of forming an integrated circuit includes forming a gate structure over a substrate. A plasma doping (PLAD) process is performed to at least a portion of the substrate that is adjacent to the gate structure. The doped portion of the substrate is annealed in an ambient with an oxygen-containing chemical.
摘要翻译：形成集成电路的方法包括在衬底上形成栅极结构。对与栅极结构相邻的衬底的至少一部分进行等离子体掺杂（PLAD）处理。衬底的掺杂部分在含氧化学物质的环境中退火。

3. 发明授权

US08796095B2 Integrated method for forming metal gate FinFET devices 有权
标题翻译：用于形成金属栅极FinFET器件的集成方法
公开(公告)号：US08796095B2
公开(公告)日：2014-08-05
申请号：US13241014
申请日：2011-09-22
申请人： Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
发明人： Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66803
摘要： Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.
摘要翻译：提供了形成在半导体鳍上的高k金属栅极结构。在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。植入操作可以在两个氮化物膜沉积操作之间进行。第一氮化物膜可以是SiNx或SiCNx，第二氮化物膜是SiCNx。可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。

4. 发明授权

US09147020B2 Transmission line characterization using EM calibration 有权
标题翻译：传输线表征使用EM校准
公开(公告)号：US09147020B2
公开(公告)日：2015-09-29
申请号：US13091803
申请日：2011-04-21
申请人： Hsiu-Ying Cho , Jiun-Kai Huang , Wen-Sheh Huang , Chin-Wei Kuo , Min-Chie Jeng
发明人： Hsiu-Ying Cho , Jiun-Kai Huang , Wen-Sheh Huang , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L23/522 , G06F17/50 , H01L21/66
CPC分类号： G06F17/5036 , H01L22/34
摘要： A method includes simulating characteristics of a first transmission line having a first length, and simulating characteristics of a second transmission line having a second length greater than the first length. A calculation is then performed on the characteristics of the first transmission line and the characteristics of the second transmission line to generate intrinsic characteristics of a third transmission line having a length equal to a difference of the second length and the first length.
摘要翻译：一种方法包括模拟具有第一长度的第一传输线的特性，以及模拟具有大于第一长度的第二长度的第二传输线的特性。然后对第一传输线的特性和第二传输线的特性执行计算，以产生具有等于第二长度和第一长度的差的长度的第三传输线的固有特性。

5. 发明授权

US08350586B2 Method and apparatus of deembedding 有权
标题翻译：去镶嵌的方法和装置
公开(公告)号：US08350586B2
公开(公告)日：2013-01-08
申请号：US12496946
申请日：2009-07-02
申请人： Shu-Ying Cho , Jiun-Kai Huang , Wen-Sheh Huang , Sally Liu
发明人： Shu-Ying Cho , Jiun-Kai Huang , Wen-Sheh Huang , Sally Liu
IPC分类号： G01R31/02 , G06F11/22 , H01L23/58
CPC分类号： G01R31/2846 , G01R31/27 , G01R31/2884 , Y10T29/49002
摘要： Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures.
摘要翻译：提供了一种去嵌入的方法。该方法包括形成具有嵌入其中的被测器件的测试结构，测试结构具有将测试器件耦合的左垫和右焊盘，被测器件分为测试结构和左半结构和右半结构，每个都具有固有的传输参数的左，右半结构; 形成多个虚拟测试结构，每个虚拟测试结构包括左垫和右垫; 测量测试结构和虚拟测试结构的传输参数; 并使用左半结构和左半结构的固有传输参数以及测试结构和虚拟测试结构的传输参数导出待测器件的固有传输参数。

6. 发明申请

US20120015493A1 INTEGRATED METHOD FOR FORMING METAL GATE FinFET DEVICES 有权
标题翻译：用于形成金属栅FinFET器件的集成方法
公开(公告)号：US20120015493A1
公开(公告)日：2012-01-19
申请号：US13241014
申请日：2011-09-22
申请人： Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
发明人： Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66803
摘要： Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.
摘要翻译：提供了形成在半导体鳍上的高k金属栅极结构。在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。植入操作可以在两个氮化物膜沉积操作之间进行。第一氮化物膜可以是SiNx或SiCNx，第二氮化物膜是SiCNx。可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。

7. 发明申请

US20110001504A1 METHOD AND APPARATUS OF DEEMBEDDING 有权
标题翻译： DEEMBEDDING的方法和设备
公开(公告)号：US20110001504A1
公开(公告)日：2011-01-06
申请号：US12496946
申请日：2009-07-02
申请人： Shu-Ying Cho , Jiun-Kai Huang , Wen-Sheh Huang , Sally Liu
发明人： Shu-Ying Cho , Jiun-Kai Huang , Wen-Sheh Huang , Sally Liu
IPC分类号： G01R31/02 , H01S4/00 , H01L21/66 , G01R31/26
CPC分类号： G01R31/2846 , G01R31/27 , G01R31/2884 , Y10T29/49002
摘要： Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures.
摘要翻译：提供了一种去嵌入的方法。该方法包括形成具有嵌入其中的被测器件的测试结构，测试结构具有将测试器件耦合的左垫和右焊盘，被测器件分为测试结构和左半结构和右半结构，每个都具有固有的传输参数的左，右半结构; 形成多个虚拟测试结构，每个虚拟测试结构包括左垫和右垫; 测量测试结构和虚拟测试结构的传输参数; 并使用左半结构和左半结构的固有传输参数以及测试结构和虚拟测试结构的传输参数来导出被测设备的固有传输参数。

8. 发明申请

US20120267626A1 Transmission Line Characterization Using EM Calibration 有权
标题翻译：使用EM校准的传输线表征
公开(公告)号：US20120267626A1
公开(公告)日：2012-10-25
申请号：US13091803
申请日：2011-04-21
申请人： Hsiu-Ying Cho , Jiun-Kai Huang , Wen-Sheh Huang , Chin-Wei Kuo , Min-Chie Jeng
发明人： Hsiu-Ying Cho , Jiun-Kai Huang , Wen-Sheh Huang , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L23/522 , H01L21/66 , G01R31/08
CPC分类号： G06F17/5036 , H01L22/34
摘要： A method includes simulating characteristics of a first transmission line having a first length, and simulating characteristics of a second transmission line having a second length greater than the first length. A calculation is then performed on the characteristics of the first transmission line and the characteristics of the second transmission line to generate intrinsic characteristics of a third transmission line having a length equal to a difference of the second length and the first length.
摘要翻译：一种方法包括模拟具有第一长度的第一传输线的特性，以及模拟具有大于第一长度的第二长度的第二传输线的特性。然后对第一传输线的特性和第二传输线的特性执行计算，以产生具有等于第二长度和第一长度的差的长度的第三传输线的固有特性。

9. 发明授权

US08187928B2 Methods of forming integrated circuits 有权
标题翻译：形成集成电路的方法
公开(公告)号：US08187928B2
公开(公告)日：2012-05-29
申请号：US12886713
申请日：2010-09-21
申请人： De-Wei Yu , Chun Hsiung Tsai , Yu-Lien Huang , Chien-Tai Chan , Wen-Sheh Huang
发明人： De-Wei Yu , Chun Hsiung Tsai , Yu-Lien Huang , Chien-Tai Chan , Wen-Sheh Huang
IPC分类号： H01L21/00 , H01L27/108
CPC分类号： H01L29/66803 , H01L21/2236 , H01L21/2253 , H01L29/7848
摘要： A method of forming an integrated circuit includes forming a gate structure over a substrate. A plasma doping (PLAD) process is performed to at least a portion of the substrate that is adjacent to the gate structure. The doped portion of the substrate is annealed in an ambient with an oxygen-containing chemical.
摘要翻译：形成集成电路的方法包括在衬底上形成栅极结构。对与栅极结构相邻的衬底的至少一部分进行等离子体掺杂（PLAD）处理。衬底的掺杂部分在含氧化学物质的环境中退火。

10. 发明授权

US08034677B2 Integrated method for forming high-k metal gate FinFET devices 有权
标题翻译：用于形成高k金属栅极FinFET器件的集成方法
公开(公告)号：US08034677B2
公开(公告)日：2011-10-11
申请号：US12712594
申请日：2010-02-25
申请人： Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
发明人： Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66803
摘要： Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiN, or SiCNx and the second nitride film is SiCNx with a low wet etch rate in H3PO4 and dilute HF acid. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.
摘要翻译：提供了形成在半导体鳍上的高k金属栅极结构。在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。在两个氮化物膜沉积操作之间进行诸如LDD或PKT注入的植入操作。第一氮化物膜可以是SiN或SiCNx，并且第二氮化物膜是在H3PO4中的低湿蚀刻速率的SiCNx和稀释的HF酸。可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。

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