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1. 发明授权

US08343872B2 Method of forming strained structures with compound profiles in semiconductor devices 有权
标题翻译：在半导体器件中形成具有复合轮廓的应变结构的方法
公开(公告)号：US08343872B2
公开(公告)日：2013-01-01
申请号：US12613714
申请日：2009-11-06
申请人： Hsueh-Chang Sung , Hsien-Hsin Lin , Kuan-Yu Chen , Chien-Chang Su , Tsz-Mei Kwok , Yi-Fang Pai
发明人： Hsueh-Chang Sung , Hsien-Hsin Lin , Kuan-Yu Chen , Chien-Chang Su , Tsz-Mei Kwok , Yi-Fang Pai
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/7834
摘要： The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material.
摘要翻译：本公开提供了一种制造方法，包括提供半导体衬底; 在基板上形成栅极结构; 执行注入工艺以在所述衬底中形成掺杂区域; 在所述栅极结构的侧壁上形成间隔物; 执行第一蚀刻以在所述衬底中形成凹部，其中所述第一蚀刻去除所述掺杂区域的一部分; 执行第二蚀刻以扩大基板中的凹部，其中第二蚀刻包括蚀刻剂和提高在掺杂区域的剩余部分处的蚀刻速率的催化剂; 并用半导体材料填充凹部。

2. 发明申请

US20110193141A1 METHOD OF FABRICATING A FINFET DEVICE 有权
标题翻译：制造FINFET器件的方法
公开(公告)号：US20110193141A1
公开(公告)日：2011-08-11
申请号：US12703918
申请日：2010-02-11
申请人： Hsien-Hsin Lin , Tsz-Mei Kwok , Chien-Chang Su
发明人： Hsien-Hsin Lin , Tsz-Mei Kwok , Chien-Chang Su
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/045 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate of a crystalline semiconductor material having a top surface of a first crystal plane orientation; a fin structure of the crystalline semiconductor material overlying the substrate; a gate structure over a portion of the fin structure; an epitaxy layer over another portion of the fin structure, the epitaxy layer having a surface having a second crystal plane orientation, wherein the epitaxy layer and underlying fin structure include a source and drain region, the source region being separated from the drain region by the gate structure; and a channel defined in the fin structure from the source region to the drain region, and aligned in a direction parallel to both the surface of the epitaxy layer and the top surface of the substrate.
摘要翻译：公开了一种用于制造FinFET器件的FinFET器件和方法。示例性的FinFET器件包括具有第一晶面取向的顶表面的晶体半导体材料的衬底; 覆盖衬底的晶体半导体材料的鳍状结构; 翅片结构的一部分上的栅极结构; 在鳍结构的另一部分上的外延层，所述外延层具有具有第二晶面取向的表面，其中所述外延层和下面的鳍结构包括源极和漏极区，源极区与漏极区分离，门结构; 以及在鳍结构中从源极区域到漏极区域限定的沟道，并且在平行于外延层的表面和衬底的顶表面的方向上排列。

3. 发明申请

US20130001705A1 Epitaxy Profile Engineering for FinFETs 审中-公开
标题翻译： FinFET的外延轮廓工程
公开(公告)号：US20130001705A1
公开(公告)日：2013-01-03
申请号：US13608961
申请日：2012-09-10
申请人： Chien-Chang Su , Tsz-Mei Kwok , Hsien-Hsin Lin , Hsueh-Chang Sung , Yi-Fang Pai , Kuan-Yu Chen
发明人： Chien-Chang Su , Tsz-Mei Kwok , Hsien-Hsin Lin , Hsueh-Chang Sung , Yi-Fang Pai , Kuan-Yu Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L21/02532 , H01L21/02636 , H01L21/823431 , H01L21/823821 , H01L29/785
摘要： A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
摘要翻译：一种形成集成电路结构的方法包括在衬底的主表面上提供包括衬底和半导体鳍片的晶片，并且执行沉积步骤以在半导体鳍片的顶表面和侧壁上外延生长外延层，其中外延层包括半导体材料。然后执行蚀刻步骤以去除外延层的一部分，其中外延层的剩余部分保留在半导体鳍片的顶表面和侧壁上。

4. 发明申请

US20110147846A1 METHOD FOR INCORPORATING IMPURITY ELEMENT IN EPI SILICON PROCESS 有权
标题翻译：在EPI硅工艺中加入污染元素的方法
公开(公告)号：US20110147846A1
公开(公告)日：2011-06-23
申请号：US12644869
申请日：2009-12-22
申请人： Chien-Chang Su , Hsien-Hsin Lin , Tsz-Mei Kwok , Kuan-Yu Chen , Hsueh-Chang Sung , Yi-Fang Pai
发明人： Chien-Chang Su , Hsien-Hsin Lin , Tsz-Mei Kwok , Kuan-Yu Chen , Hsueh-Chang Sung , Yi-Fang Pai
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/7851 , H01L21/02532 , H01L21/02573 , H01L21/02576 , H01L21/0262 , H01L29/0653 , H01L29/167 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括形成多个翅片，翅片通过隔离结构彼此隔离，在每个翅片的一部分上形成栅极结构; 在栅极结构的侧壁上分别形成间隔物，蚀刻每个鳍片的剩余部分，从而形成凹槽，外延生长硅以填充凹槽，包括掺杂选自锗（Ge），铟（In），和碳（C），并用n型掺杂剂掺杂硅epi。

5. 发明申请

US20110073952A1 Controlling the Shape of Source/Drain Regions in FinFETs 有权
标题翻译：控制FinFET中源极/漏极区域的形状
公开(公告)号：US20110073952A1
公开(公告)日：2011-03-31
申请号：US12831925
申请日：2010-07-07
申请人： Tsz-Mei Kwok , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Hsien-Hsin Lin
发明人： Tsz-Mei Kwok , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Hsien-Hsin Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L21/76 , H01L29/045 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.
摘要翻译：集成电路结构包括鳍状物场效应晶体管（FinFET），其包括在绝缘区域上方并邻近绝缘区域的半导体鳍片; 以及绝缘区域上的源极/漏极区域。源极/漏极区域包括第一和第二半导体区域。第一半导体区域包括硅和选自锗和碳的元素，其中元素在第一半导体区域中具有第一原子百分比。第一半导体区域具有上斜面和向下斜面。第二半导体区域包括硅和元件。该元素具有比第一原子百分比低的第二原子百分比。第二半导体区域在上斜面上具有第一部分，并具有第一厚度。第二半导体区域的第二部分（如果有的话）在下斜面上具有小于第一厚度的第二厚度。

6. 发明授权

US08487354B2 Method for improving selectivity of epi process 有权
标题翻译：提高epi过程选择性的方法
公开(公告)号：US08487354B2
公开(公告)日：2013-07-16
申请号：US12545705
申请日：2009-08-21
申请人： Kuan-Yu Chen , Hsien-Hsin Lin , Chun-Feng Nieh , Hsueh-Chang Sung , Chien-Chang Su , Tsz-Mei Kwok
发明人： Kuan-Yu Chen , Hsien-Hsin Lin , Chun-Feng Nieh , Hsueh-Chang Sung , Chien-Chang Su , Tsz-Mei Kwok
IPC分类号： H01L29/76
CPC分类号： H01L29/66477 , H01L21/31116 , H01L21/31155 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process.
摘要翻译：本公开提供一种制造半导体器件的方法，其包括提供半导体衬底，在衬底上形成栅极结构，在衬底上形成材料层和栅极结构，将Ge，C，P，F或B注入所述材料层，去除所述栅极结构的任一侧上覆盖所述衬底的所述材料层的部分，在所述栅极结构的任一侧上在所述衬底中形成凹陷，以及通过开晶过程在所述凹部中沉积半导体材料。

7. 发明授权

US08263451B2 Epitaxy profile engineering for FinFETs 有权
标题翻译： FinFET的外延轮廓工程
公开(公告)号：US08263451B2
公开(公告)日：2012-09-11
申请号：US12713573
申请日：2010-02-26
申请人： Chien-Chang Su , Tsz-Mei Kwok , Hsien-Hsin Lin , Hsueh-Chang Sung , Yi-Fang Pai , Kuan-Yu Chen
发明人： Chien-Chang Su , Tsz-Mei Kwok , Hsien-Hsin Lin , Hsueh-Chang Sung , Yi-Fang Pai , Kuan-Yu Chen
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/66795 , H01L21/02532 , H01L21/02636 , H01L21/823431 , H01L21/823821 , H01L29/785
摘要： A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
摘要翻译：一种形成集成电路结构的方法包括在衬底的主表面上提供包括衬底和半导体鳍片的晶片，并且执行沉积步骤以在半导体鳍片的顶表面和侧壁上外延生长外延层，其中外延层包括半导体材料。然后执行蚀刻步骤以去除外延层的一部分，其中外延层的剩余部分保留在半导体鳍片的顶表面和侧壁上。

8. 发明申请

US20110042729A1 METHOD FOR IMPROVING SELECTIVITY OF EPI PROCESS 有权
标题翻译：改进EPI过程选择性的方法
公开(公告)号：US20110042729A1
公开(公告)日：2011-02-24
申请号：US12545705
申请日：2009-08-21
申请人： Kuan-Yu Chen , Hsien-Hsin Lin , Chun-Feng Nieh , Hsueh-Chang Sung , Chien-Chang Su , Tsz-Mei Kwok
发明人： Kuan-Yu Chen , Hsien-Hsin Lin , Chun-Feng Nieh , Hsueh-Chang Sung , Chien-Chang Su , Tsz-Mei Kwok
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/66477 , H01L21/31116 , H01L21/31155 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process.
摘要翻译：本公开提供一种制造半导体器件的方法，其包括提供半导体衬底，在衬底上形成栅极结构，在衬底上形成材料层和栅极结构，将Ge，C，P，F或B注入所述材料层，去除所述栅极结构的任一侧上覆盖所述衬底的所述材料层的部分，在所述栅极结构的任一侧上在所述衬底中形成凹陷，以及通过开晶过程在所述凹部中沉积半导体材料。

9. 发明授权

US09666691B2 Epitaxy profile engineering for FinFETs 有权
公开(公告)号：US09666691B2
公开(公告)日：2017-05-30
申请号：US13608961
申请日：2012-09-10
申请人： Chien-Chang Su , Tsz-Mei Kwok , Hsien-Hsin Lin , Hsueh-Chang Sung , Yi-Fang Pai , Kuan-Yu Chen
发明人： Chien-Chang Su , Tsz-Mei Kwok , Hsien-Hsin Lin , Hsueh-Chang Sung , Yi-Fang Pai , Kuan-Yu Chen
IPC分类号： H01L27/088 , H01L29/66 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L21/02
CPC分类号： H01L29/66795 , H01L21/02532 , H01L21/02636 , H01L21/823431 , H01L21/823821 , H01L29/785
摘要： A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

10. 发明授权

US08362575B2 Controlling the shape of source/drain regions in FinFETs 有权
公开(公告)号：US08362575B2
公开(公告)日：2013-01-29
申请号：US12831925
申请日：2010-07-07
申请人： Tsz-Mei Kwok , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Hsien-Hsin Lin
发明人： Tsz-Mei Kwok , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Hsien-Hsin Lin
IPC分类号： H01L27/088 , H01L21/70 , H01L21/02 , H01L29/06 , H01L29/04 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/7851 , H01L21/76 , H01L29/045 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

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