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11. 发明授权

US07601646B2 Top-oxide-early process and array top oxide planarization 有权
标题翻译：顶部氧化物早期过程和阵列顶部氧化物平面化
公开(公告)号：US07601646B2
公开(公告)日：2009-10-13
申请号：US10710566
申请日：2004-07-21
申请人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
发明人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
IPC分类号： H01L21/3065 , H01L21/308 , H01L21/311
CPC分类号： H01L27/10894 , H01L21/31053 , H01L27/10841 , H01L27/10897
摘要： Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.
摘要翻译：通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部氧化物晚期过程。新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

12. 发明申请

US20060019443A1 TOP-OXIDE-EARLY PROCESS AND ARRAY TOP OXIDE PLANARIZATION 有权
标题翻译：前氧化物早期工艺和顶部氧化物平面排列
公开(公告)号：US20060019443A1
公开(公告)日：2006-01-26
申请号：US10710566
申请日：2004-07-21
申请人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
发明人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
IPC分类号： H01L21/467 , H01L21/8242
CPC分类号： H01L27/10894 , H01L21/31053 , H01L27/10841 , H01L27/10897
摘要： Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.
摘要翻译：通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部氧化物晚期过程。新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

13. 发明授权

US06957589B2 Temperature compensator of torque sensor 失效
标题翻译：扭矩传感器的温度补偿器
公开(公告)号：US06957589B2
公开(公告)日：2005-10-25
申请号：US10639857
申请日：2003-08-13
申请人： Takayuki Ueno , Hiroyuki Akatsu
发明人： Takayuki Ueno , Hiroyuki Akatsu
IPC分类号： G01L25/00 , G01L3/02 , G01L3/10
CPC分类号： G01L3/105
摘要： The present invention provides a temperature compensator for a torque sensor, including a pair of coils, which are connected to an AC power supply circuit via transistors and in which inductances change in opposite directions depending on torque, and a torque detecting means which obtains a voltage difference between a first voltage and a second voltage output via smoothing circuits based on changes in inductance of each pair of coils, and outputs as a torque detection voltage, the temperature compensator having a correcting voltage extracting means for extracting a voltage between terminals of a transistor in the AC power supply circuit as a temperature correcting voltage, and a correcting means for correcting the torque detection voltage based on a temperature correcting voltage Vs extracted by the correcting voltage extracting means.
摘要翻译：本发明提供了一种用于扭矩传感器的温度补偿器，包括一对线圈，其经由晶体管连接到AC电源电路，并且其中电感根据转矩沿相反方向变化;以及转矩检测装置，其获得电压基于每对线圈的电感的变化，通过平滑电路输出的第一电压和第二电压之间的差，并且作为转矩检测电压输出，所述温度补偿器具有校正电压提取装置，用于提取晶体管的端子之间的电压在作为温度校正电压的交流电源电路中，以及校正装置，用于基于由校正电压提取装置提取的温度校正电压Vs来校正转矩检测电压。

14. 发明申请

US20050184359A1 STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR 有权
标题翻译：带有收集器的自对准双极晶体管的结构和方法
公开(公告)号：US20050184359A1
公开(公告)日：2005-08-25
申请号：US10708340
申请日：2004-02-25
申请人： Hiroyuki Akatsu , Rama Divakaruni , Gregory Freeman , David Greenberg , Marwan Khater , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Gregory Freeman , David Greenberg , Marwan Khater , William Tonti
IPC分类号： H01L21/331 , H01L27/082 , H01L29/08 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.
摘要翻译：提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积下表面。双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

15. 发明授权

US06849153B2 Removal of post-rie polymer on A1/CU metal line 有权
标题翻译：去除A1 / CU金属线上的后聚合物
公开(公告)号：US06849153B2
公开(公告)日：2005-02-01
申请号：US09204706
申请日：1998-12-03
申请人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
发明人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
IPC分类号： H01L21/302 , G03F7/42 , H01L21/02 , H01L21/027 , H01L21/306 , H01L21/3065 , H01L21/3205 , H01L21/3213 , C23F1/08
CPC分类号： H01L21/02071 , H01L21/02054 , H01L21/31138 , H01L21/32136 , Y10S134/902
摘要： A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising: 1) supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber in which said composite structure is supported to form a water soluble material of sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; removing the water soluble material with deionized water; and removing photo-resist from said composite structure by either a water-only plasma process or a chemical down stream etching method; or 2) forming a water-only plasma process to strip the photo-resist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE process; supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber on which said structure is supported to form a water soluble material of saidwall polymer rails left behind on the Al/Cu metal line from the RIE process; and removing the water soluble material with deionized water.
摘要翻译：一种用于去除在半导体或微电子复合结构的Al / Cu金属线上的反应活性离子蚀刻侧壁聚合物轨道的方法，包括：1）将蚀刻气体和酸中和气体的混合物供应到真空室中，其中所述复合材料结构被支撑以形成从RIE工艺在Al / Cu金属线上留下的侧壁聚合物轨道的水溶性材料; 用去离子水去除水溶性物质; 以及通过水纯等离子体工艺或化学下游蚀刻方法从所述复合结构中除去光致抗蚀剂; 或2）形成仅水性等离子体工艺以剥离先前经受RIE工艺的半导体或微电子复合结构的光致抗蚀剂层;将蚀刻气体和酸中和气体的混合物供应到真空室中，在真空室中，被支撑以形成从RIE工艺在Al / Cu金属线上留下的所述壁聚合物轨道的水溶性材料; 并用去离子水去除水溶性物质。

16. 发明授权

US06723611B2 Vertical hard mask 失效
标题翻译：垂直硬面罩
公开(公告)号：US06723611B2
公开(公告)日：2004-04-20
申请号：US10241225
申请日：2002-09-10
申请人： Hiroyuki Akatsu , Oleg Gluschenkov , Porshia S. Parkinson , Ravikumar Ramachandran , Helmut Horst Tews , Kenneth T. Settlemyer, Jr.
发明人： Hiroyuki Akatsu , Oleg Gluschenkov , Porshia S. Parkinson , Ravikumar Ramachandran , Helmut Horst Tews , Kenneth T. Settlemyer, Jr.
IPC分类号： H01L2120
CPC分类号： H01L27/1087
摘要： In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.
摘要翻译：在形成沟槽电容器或类似结构的过程中，衬底中的孔的侧壁衬有包含扩散阻挡层的膜堆叠; 外层的上部被剥离，使得上部和下部具有不同的材料暴露; 薄膜堆叠的下部被剥离，同时上部被硬掩模层保护; 在上部被保护的同时在下部进行扩散步骤; 并且选择性地将选择的材料如半球形硅沉积在下部上，而上部的暴露表面是选择的材料形成不良的材料，使得扩散材料渗透，并且所选择的材料仅形成在下部。

17. 发明授权

US06379577B2 Hydrogen peroxide and acid etchant for a wet etch process 失效
标题翻译：用于湿蚀刻工艺的过氧化氢和酸蚀刻剂
公开(公告)号：US06379577B2
公开(公告)日：2002-04-30
申请号：US09329894
申请日：1999-06-10
申请人： Hiroyuki Akatsu , David E. Kotecki , Jingyu Jenny Lian , Hua Shen
发明人： Hiroyuki Akatsu , David E. Kotecki , Jingyu Jenny Lian , Hua Shen
IPC分类号： H01L21302
CPC分类号： C04B41/009 , C04B41/5353 , C04B41/91 , C04B2111/00853 , H01L21/31111 , C04B35/465 , C04B35/472
摘要： A process and solution for selectively wet etching a titanium based perovskite material disposed on a silicon oxide or silicon nitride substrate is disclosed herein. The solution is composed of hydrogen peroxide, an acid and deionized water. The solution is heated to a temperature between 25 and 90 degrees Celsius. The titanium based perovskite material may be barium strontium titanate, barium titanate, strontium titanate or a lead titanate. The solution selectively etches the perovskite material while the substrate is only minimally etched, if at all. The process and solution allows for an etching rate up to thirty times greater than conventional etching rates for similar perovskite materials selective to various substrate, barrier and mask layers, including SiO2.
摘要翻译：本文公开了用于选择性湿蚀刻设置在氧化硅或氮化硅衬底上的钛基钙钛矿材料的工艺和解决方案。溶液由过氧化氢，酸和去离子水组成。将溶液加热至25至90摄氏度之间的温度。钛基钙钛矿材料可以是钛酸锶钡，钛酸钡，钛酸锶或钛酸铅。该方案选择性地蚀刻钙钛矿材料，同时基板仅被最小蚀刻，如果有的话。该方法和解决方案允许对于包括SiO 2的各种衬底，阻挡层和掩模层选择性的类似钙钛矿材料，蚀刻速率高达常规蚀刻速率的三十倍。

18. 发明授权

US06329704B1 Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer 失效
标题翻译：在介电层内具有峰值浓度的超浅结掺杂剂层
公开(公告)号：US06329704B1
公开(公告)日：2001-12-11
申请号：US09458530
申请日：1999-12-09
申请人： Hiroyuki Akatsu , Omer H. Dokumaci , Suryanarayan G. Hegde , Yujun Li , Rajesh Rengarajan , Paul A. Ronsheim
发明人： Hiroyuki Akatsu , Omer H. Dokumaci , Suryanarayan G. Hegde , Yujun Li , Rajesh Rengarajan , Paul A. Ronsheim
IPC分类号： H01L29167
CPC分类号： H01L21/2652 , H01L21/2254 , H01L21/2255 , H01L29/6659
摘要： A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.
摘要翻译：一种用于在硅衬底内形成超浅结深度掺杂区的工艺。该方法包括在衬底上形成电介质膜，然后将离子掺杂剂物质注入结构中。植入物种的轮廓包括通过电介质膜注入硅衬底中的群体，以及刻意限制在电介质膜中的接近于介电膜和硅衬底之间界面的峰值浓度。使用高能量，低剂量的植入工艺，并且产生基本上不含位错环和其它缺陷簇的结构。使用退火工艺来驱动更接近界面的峰值浓度，以及从电介质膜到硅衬底的最初注入物质的一些群体。由于植入的峰浓度与界面的接近以及通过电介质膜注入并进入衬底的物质的存在，维持了低热量预算。

19. 发明授权

US06297530B1 Self aligned channel implantation 失效
标题翻译：自对准通道植入
公开(公告)号：US06297530B1
公开(公告)日：2001-10-02
申请号：US09418181
申请日：1998-12-28
申请人： Hiroyuki Akatsu , Yujun Li , Jochen Beintner
发明人： Hiroyuki Akatsu , Yujun Li , Jochen Beintner
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/823412 , H01L29/105
摘要： A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.
摘要翻译：短沟道绝缘栅场效应晶体管在半导体本体内部具有与晶体管相同的导电类型的掩埋层，但具有较高的杂质浓度。掩埋层在沟道区下方，并且基本上只延伸晶体管的漏极和源极区之间的距离。形成器件的过程在栅极下方的区域提供高浓度，以抑制横向耗尽区域膨胀，同时保持垂直方向上的逐渐连接。

20. 发明授权

US08655696B2 System for performing schedule management, schedule management method and program 失效
标题翻译：用于执行进度管理，进度管理方法和程序的系统
公开(公告)号：US08655696B2
公开(公告)日：2014-02-18
申请号：US12354671
申请日：2009-01-15
申请人： Hiroyuki Akatsu , Atsushi Fukuda , Takashi Nerome , Masayuki Numao
发明人： Hiroyuki Akatsu , Atsushi Fukuda , Takashi Nerome , Masayuki Numao
IPC分类号： G06Q10/00 , G06G1/12
CPC分类号： G06Q10/10 , G06Q10/06 , G06Q10/06311
摘要： A system includes a structure information obtaining unit which obtains structure information containing information on components of a development target in a project and on dependency relationships between the components, the structure information described, e.g., in SysML, a work item determining unit which determines work items and a work execution order based on the structure information obtained by the structure information obtaining unit; a detailed item determining unit; a date scheduling unit and a WBS storage which manages the determined work items and work execution order as work schedule definition information. The work item determining unit determines a work item related to a leaf component, which is a component not including any other component, and determines, in a case where all of the multiple components included in a single predetermined component are leaf components, a work item related to a coupling relationship between the leaf components.
摘要翻译：一种系统，包括结构信息获取单元，其获得包含项目中的开发目标的组件的信息的结构信息以及组件之间的依赖关系，例如在SysML中描述的结构信息，确定工作项目的工作项确定单元以及基于由结构信息获取单元获得的结构信息的工作执行顺序; 详细项目确定单元; 日历调度单元和WBS存储器，其将确定的工作项目和工作执行顺序作为工作调度定义信息进行管理。工作项确定单元确定与不包括任何其他组件的组件相关的工作项，并且在包括在单个预定组件中的所有多个组件都是叶组件的情况下确定工作项与叶分量之间的耦合关系有关。

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