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1. 发明授权

US06849153B2 Removal of post-rie polymer on A1/CU metal line 有权
标题翻译：去除A1 / CU金属线上的后聚合物
公开(公告)号：US06849153B2
公开(公告)日：2005-02-01
申请号：US09204706
申请日：1998-12-03
申请人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
发明人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
IPC分类号： H01L21/302 , G03F7/42 , H01L21/02 , H01L21/027 , H01L21/306 , H01L21/3065 , H01L21/3205 , H01L21/3213 , C23F1/08
CPC分类号： H01L21/02071 , H01L21/02054 , H01L21/31138 , H01L21/32136 , Y10S134/902
摘要： A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising: 1) supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber in which said composite structure is supported to form a water soluble material of sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; removing the water soluble material with deionized water; and removing photo-resist from said composite structure by either a water-only plasma process or a chemical down stream etching method; or 2) forming a water-only plasma process to strip the photo-resist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE process; supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber on which said structure is supported to form a water soluble material of saidwall polymer rails left behind on the Al/Cu metal line from the RIE process; and removing the water soluble material with deionized water.
摘要翻译：一种用于去除在半导体或微电子复合结构的Al / Cu金属线上的反应活性离子蚀刻侧壁聚合物轨道的方法，包括：1）将蚀刻气体和酸中和气体的混合物供应到真空室中，其中所述复合材料结构被支撑以形成从RIE工艺在Al / Cu金属线上留下的侧壁聚合物轨道的水溶性材料; 用去离子水去除水溶性物质; 以及通过水纯等离子体工艺或化学下游蚀刻方法从所述复合结构中除去光致抗蚀剂; 或2）形成仅水性等离子体工艺以剥离先前经受RIE工艺的半导体或微电子复合结构的光致抗蚀剂层;将蚀刻气体和酸中和气体的混合物供应到真空室中，在真空室中，被支撑以形成从RIE工艺在Al / Cu金属线上留下的所述壁聚合物轨道的水溶性材料; 并用去离子水去除水溶性物质。

2. 发明授权

US5980770A Removal of post-RIE polymer on Al/Cu metal line 失效
标题翻译：在Al / Cu金属线上去除RIE后聚合物
公开(公告)号：US5980770A
公开(公告)日：1999-11-09
申请号：US061565
申请日：1998-04-16
申请人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
发明人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
IPC分类号： H01L21/302 , H01L21/02 , H01L21/3213 , C03C25/06 , C23F1/12
CPC分类号： H01L21/02071 , H01L21/31138 , H01L21/32136 , Y10S438/906
摘要： A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising:1) supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber in which said composite structure is supported to form a water soluble material of sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; removing the water soluble material with deionized water; and removing photo-resist from said composite structure by either a water-only plasma process or a chemical down stream etching method; or2) forming a water-only plasma process to strip the photo-resist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE process;supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber on which said structure is supported to form a water soluble material of saidwall polymer rails left behind on the Al/Cu metal line from the RIE process; andremoving the water soluble material with deionized water.
摘要翻译：一种用于去除在半导体或微电子复合结构的Al / Cu金属线上的反应活性离子蚀刻侧壁聚合物轨道的方法，包括：1）将蚀刻气体和酸中和气体的混合物供应到真空室中，其中所述复合材料结构被支撑以形成从RIE工艺在Al / Cu金属线上留下的侧壁聚合物轨道的水溶性材料; 用去离子水去除水溶性物质; 以及通过水纯等离子体工艺或化学下游蚀刻方法从所述复合结构中除去光致抗蚀剂; 或2）形成仅水等离子体工艺以剥离先前经过RIE工艺的半导体或微电子复合结构的光致抗蚀剂层; 将一种蚀刻气体和酸中和气体的混合物供给到所述结构被支撑的真空室中，以形成从RIE工艺在Al / Cu金属管线上留下的所述壁聚合物轨道的水溶性材料; 并用去离子水除去水溶性物质。

3. 发明授权

US5932493A Method to minimize watermarks on silicon substrates 失效
标题翻译：最小化硅衬底上的水印的方法
公开(公告)号：US5932493A
公开(公告)日：1999-08-03
申请号：US929590
申请日：1997-09-15
申请人： Hiroyuki Akatsu , Ronald Hoyer , Ravikumar Ramachandran
发明人： Hiroyuki Akatsu , Ronald Hoyer , Ravikumar Ramachandran
IPC分类号： H01L21/304 , H01L21/306 , H01L21/00
CPC分类号： H01L21/02052
摘要： Formation of watermarks during semiconductor processing can be prevented by rinsing silicon wafers in an organic solvent prior to drying. Water droplets on the silicon wafer surface are taken up by the solvent and film is formed over the wafer surface. Following this rinse, the wafer may be subjected to standard IPA-based drying techniques.
摘要翻译：可以通过在干燥之前冲洗有机溶剂中的硅晶片来防止在半导体加工期间形成水印。硅晶片表面上的水滴被溶剂吸收，并且在晶片表面上形成膜。在该冲洗之后，可以对晶片进行标准的基于IPA的干燥技术。

4. 发明授权

US5807439A Apparatus and method for improved washing and drying of semiconductor wafers 失效
公开(公告)号：US5807439A
公开(公告)日：1998-09-15
申请号：US939547
申请日：1997-09-29
申请人： Hiroyuki Akatsu , Ravikumar Ramachandran
发明人： Hiroyuki Akatsu , Ravikumar Ramachandran
IPC分类号： H01L21/304 , H01L21/00 , F26B7/00
CPC分类号： H01L21/67028 , H01L21/67023 , Y10S134/902
摘要： Apparatus and method are provided for improved washing and drying of semiconductor wafers utilizing an enhanced "Marangoni effect" flow of liquid off of the wafers for superior prevention of watermarks (water spots) on integrated circuits (ICs) on the wafers. The apparatus includes a housing 12 which may be hermetically sealed, an open-top wash tank 60 within a lower part of the housing, a moveable rack 16 for holding the wafers either in the tank for washing or in an upper part of the housing for drying, apparatus 34 for supplying chilled (near freezing) de-ionized water (DIW) to a lower part of the tank, the DIW flowing within the tank and overflowing the top thereof, a pump 20 for draining overflowing DIW from the housing, and apparatus 40 for supplying to the housing organic vapor such as isopropyl alcohol (IPA) in a dry gas such as nitrogen. During wafer drying operation of the apparatus the pressure within the housing is kept at about one Torr or less.

5. 发明授权

US06723611B2 Vertical hard mask 失效
标题翻译：垂直硬面罩
公开(公告)号：US06723611B2
公开(公告)日：2004-04-20
申请号：US10241225
申请日：2002-09-10
申请人： Hiroyuki Akatsu , Oleg Gluschenkov , Porshia S. Parkinson , Ravikumar Ramachandran , Helmut Horst Tews , Kenneth T. Settlemyer, Jr.
发明人： Hiroyuki Akatsu , Oleg Gluschenkov , Porshia S. Parkinson , Ravikumar Ramachandran , Helmut Horst Tews , Kenneth T. Settlemyer, Jr.
IPC分类号： H01L2120
CPC分类号： H01L27/1087
摘要： In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.
摘要翻译：在形成沟槽电容器或类似结构的过程中，衬底中的孔的侧壁衬有包含扩散阻挡层的膜堆叠; 外层的上部被剥离，使得上部和下部具有不同的材料暴露; 薄膜堆叠的下部被剥离，同时上部被硬掩模层保护; 在上部被保护的同时在下部进行扩散步骤; 并且选择性地将选择的材料如半球形硅沉积在下部上，而上部的暴露表面是选择的材料形成不良的材料，使得扩散材料渗透，并且所选择的材料仅形成在下部。

6. 发明授权

US5934299A Apparatus and method for improved washing and drying of semiconductor wafers 失效
标题翻译：用于改善半导体晶片的洗涤和干燥的装置和方法
公开(公告)号：US5934299A
公开(公告)日：1999-08-10
申请号：US95985
申请日：1998-06-11
申请人： Hiroyuki Akatsu , Ravikumar Ramachandran
发明人： Hiroyuki Akatsu , Ravikumar Ramachandran
IPC分类号： H01L21/304 , H01L21/00 , B08B3/00
CPC分类号： H01L21/67028 , H01L21/67023 , Y10S134/902
摘要： Apparatus and method are provided for improved washing and drying of semiconductor wafers utilizing an enhanced "Marangoni effect" flow of liquid off of the wafers for superior prevention of watermarks (water spots) on integrated circuits (ICs) on the wafers. The apparatus includes a housing 12 which may be hermetically sealed, an open-top wash tank 60 within a lower part of the housing, a moveable rack 16 for holding the wafers either in the tank for washing or in an upper part of the housing for drying, apparatus 34 for supplying chilled (near freezing) de-ionized water (DIW) to a lower part of the tank, the DIW flowing within the tank and overflowing the top thereof, a pump 20 for draining overflowing DIW from the housing, and apparatus 40 for supplying to the housing organic vapor such as isopropyl alcohol (IPA) in a dry gas such as nitrogen. During wafer drying operation of the apparatus the pressure within the housing is kept at about one Torr or less.
摘要翻译：提供了用于利用晶片的液体增强的“马兰戈尼效应”流动来改善半导体晶片的洗涤和干燥的装置和方法，以优越地防止晶片上的集成电路（IC）上的水印（水斑）。该装置包括可以气密密封的壳体12，在壳体的下部内的开放式清洗罐60，用于将晶片保持在用于洗涤的罐中或在壳体的上部中的可移动的支架16 干燥装置34，用于向罐的下部供应冷冻（近冷冻）去离子水（DIW），DIW在罐内流动并溢出其顶部;泵20，用于从壳体排出溢流的DIW;以及用于在诸如氮气的干燥气体中供应到壳体有机蒸气如异丙醇（IPA）的装置40。在设备的晶片干燥操作期间，壳体内的压力保持在约1托或更低。

7. 发明授权

US06887761B1 Vertical semiconductor devices 失效
标题翻译：垂直半导体器件
公开(公告)号：US06887761B1
公开(公告)日：2005-05-03
申请号：US10708647
申请日：2004-03-17
申请人： Hiroyuki Akatsu , Thomas W. Dyer , Ravikumar Ramachandran , Kenneth T. Settlemyer, Jr.
发明人： Hiroyuki Akatsu , Thomas W. Dyer , Ravikumar Ramachandran , Kenneth T. Settlemyer, Jr.
IPC分类号： H01L21/336 , H01L21/762 , H01L29/78 , H01I29/76
CPC分类号： H01L29/66666 , H01L21/2257 , H01L21/76224 , H01L29/7827
摘要： A method and structure for increasing the threshold voltage of vertical semiconductor devices. The method comprises creating a deep trench in a substrate whose semiconductor material has an orientation plane perpendicular to the surface of the substrate. Then, vertical transistors are formed around and along the depth of the deep trench. Next, two shallow trench isolation are formed such that they sandwich the deep trench in an active region and the two shallow trench isolation regions abut the active region via planes perpendicular to the orientation plane. Then, the channel regions of the vertical transistors are exposed to the atmosphere in the deep trench and then chemically etched to planes parallel to the orientation plane. Then, a gate dielectric layer is formed on the wall of the deep trench. Finally, the deep trench is filled with poly-silicon to form the gate for the vertical transistors.
摘要翻译：一种用于增加垂直半导体器件的阈值电压的方法和结构。该方法包括在其半导体材料具有垂直于衬底表面的取向平面的衬底中形成深沟槽。然后，在深沟槽的深度周围形成垂直晶体管。接下来，形成两个浅沟槽隔离，使得它们在有源区域中夹住深沟槽，并且两个浅沟槽隔离区域经由垂直于取向平面的平面邻接有源区。然后，垂直晶体管的沟道区域暴露在深沟槽中的大气中，然后化学蚀刻到平行于取向平面的平面上。然后，在深沟槽的壁上形成栅极电介质层。最后，深沟槽充满多晶硅，形成垂直晶体管的栅极。

8. 发明申请

US20100332444A1 AUTOMATIC DESIGNING SYSTEM, AUTOMATIC DESIGNING METHOD AND AUTOMATIC DESIGNING PROGRAM FOR AUTOMATICALLY DESIGNING ARCHITECTURE FOR SYSTEM COMPONENTS 失效
标题翻译：自动设计系统，自动设计方法和自动设计系统组件结构自动设计程序
公开(公告)号：US20100332444A1
公开(公告)日：2010-12-30
申请号：US12825830
申请日：2010-06-29
申请人： Hiroyuki Akatsu , Hisashi Miyashita , Hiroaki Nakamura , Takashi Nerome
发明人： Hiroyuki Akatsu , Hisashi Miyashita , Hiroaki Nakamura , Takashi Nerome
IPC分类号： G06N5/02 , G06G7/48
CPC分类号： G06N5/025 , G06F17/5095
摘要： An automatic designing system includes: a rule storage unit storing sets of rewrite rules for rewriting variable nodes of a hierarchically structured graph in a design architecture for the system; a search unit sequentially determining variable nodes as application targets for the rewrite rules by searching the graph, including components in the design architecture for the system to be designed, using a search tree; a judgment unit judging whether the rewrite rule is applicable to the determined variable node; and a rule application unit replacing the determined variable node with a partial graph, including at least one of fixed and variable nodes, according to the rewrite rule, in response to a judgment that the rewrite rule is applicable. The search unit performs the searching until an undefined variable node no longer exists in the graph to be designed, and performs backtracking on condition that no variable node is found.
摘要翻译：自动设计系统包括：规则存储单元，用于存储用于重构用于系统的设计架构中用于重写分层结构化图形的可变节点的重写规则; 搜索单元使用搜索树通过搜索包括要设计的系统的设计架构中的组件的图来顺序地将变量节点确定为重写规则的应用目标; 判断单元判断所述重写规则是否适用于所确定的变量节点; 以及规则应用单元，响应于可重写规则的判断，根据重写规则，用包括固定节点和可变节点中的至少一个的部分图替换确定的变量节点。搜索单元执行搜索，直到要设计的图中不再存在未定义的变量节点，并且在没有找到变量节点的条件下执行回溯。

9. 发明申请

US20080052144A1 SYSTEM AND METHOD FOR MANAGING WORKFLOW 失效
标题翻译：用于管理工作流的系统和方法
公开(公告)号：US20080052144A1
公开(公告)日：2008-02-28
申请号：US11776151
申请日：2007-07-11
申请人： Hiroyuki Akatsu , Kenji Eda , Yo Murai , Teruaki Okano , Yasuharu Yada , Masao Yamada
发明人： Hiroyuki Akatsu , Kenji Eda , Yo Murai , Teruaki Okano , Yasuharu Yada , Masao Yamada
IPC分类号： G06F9/46
CPC分类号： G06Q10/06 , G06Q10/063 , G06Q10/0633
摘要： A system and method for managing a workflow are provided. A system for managing a workflow in accordance with an embodiment of the invention includes: a storage unit for storing, as an access history for each of at least one artifact, identification information of a business process that has accessed the artifact; a request reception unit for receiving an access request to an artifact from a user; a first notification unit for retrieving an access history corresponding to a first artifact from the storage unit on a condition that a first access request received from the user corresponding to a first business process is an update request of the first artifact, and for notifying a user corresponding to the business process that is identified in the retrieved access history that the first artifact is to be updated; and a history adding unit for adding identification information of the first business process to the access history corresponding to the first artifact in response to an accessing of the first artifact based on the first access request.
摘要翻译：提供了一种用于管理工作流的系统和方法。根据本发明的实施例的用于管理工作流的系统包括：存储单元，用于存储已访问所述工件的业务处理的识别信息作为至少一个工件中的每一个的访问历史; 请求接收单元，用于从用户接收对工件的访问请求; 第一通知单元，用于在从与第一业务处理对应的用户接收到的第一访问请求是第一伪像的更新请求的条件下从存储单元检索与第一伪像相对应的访问历史，并且用于通知用户对应于在检索的访问历史中识别出的第一个工件将被更新的业务流程; 以及历史添加单元，用于响应于基于第一访问请求访问第一伪像，将第一业务处理的标识信息添加到与第一伪像相对应的访问历史。

10. 发明授权

US07190046B2 Bipolar transistor having reduced collector-base capacitance 失效
标题翻译：双极晶体管具有降低的集电极 - 基极电容
公开(公告)号：US07190046B2
公开(公告)日：2007-03-13
申请号：US10708860
申请日：2004-03-29
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
IPC分类号： H01L27/082 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.
摘要翻译：提供了用于形成双极晶体管的结构和方法。如所公开的，提供覆盖在集电极层上的本征基层。低电容区域横向设置在集电极层附近。低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。

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