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1. 发明授权

US06723611B2 Vertical hard mask 失效
标题翻译：垂直硬面罩
公开(公告)号：US06723611B2
公开(公告)日：2004-04-20
申请号：US10241225
申请日：2002-09-10
申请人： Hiroyuki Akatsu , Oleg Gluschenkov , Porshia S. Parkinson , Ravikumar Ramachandran , Helmut Horst Tews , Kenneth T. Settlemyer, Jr.
发明人： Hiroyuki Akatsu , Oleg Gluschenkov , Porshia S. Parkinson , Ravikumar Ramachandran , Helmut Horst Tews , Kenneth T. Settlemyer, Jr.
IPC分类号： H01L2120
CPC分类号： H01L27/1087
摘要： In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.
摘要翻译：在形成沟槽电容器或类似结构的过程中，衬底中的孔的侧壁衬有包含扩散阻挡层的膜堆叠; 外层的上部被剥离，使得上部和下部具有不同的材料暴露; 薄膜堆叠的下部被剥离，同时上部被硬掩模层保护; 在上部被保护的同时在下部进行扩散步骤; 并且选择性地将选择的材料如半球形硅沉积在下部上，而上部的暴露表面是选择的材料形成不良的材料，使得扩散材料渗透，并且所选择的材料仅形成在下部。

2. 发明授权

US06555430B1 Process flow for capacitance enhancement in a DRAM trench 失效
标题翻译： DRAM沟槽中电容增强的工艺流程
公开(公告)号：US06555430B1
公开(公告)日：2003-04-29
申请号：US09723420
申请日：2000-11-28
申请人： Michael P. Chudzik , Johnathan Faltermeier , Rajarao Jammy , Stephan Kudelka , Irene McStay , Kenneth T. Settlemyer, Jr. , Helmut Horst Tews
发明人： Michael P. Chudzik , Johnathan Faltermeier , Rajarao Jammy , Stephan Kudelka , Irene McStay , Kenneth T. Settlemyer, Jr. , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L28/84 , Y10S438/964
摘要： Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.
摘要翻译：提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。一种方法包括以下步骤：在下沟槽区域的暴露的壁上形成不连续的多晶硅层，所述不连续的多晶硅层在其中具有暴露所述衬底的部分的间隙; 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续的多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽。

3. 发明授权

US06358867B1 Orientation independent oxidation of silicon 有权
标题翻译：硅取向独立氧化
公开(公告)号：US06358867B1
公开(公告)日：2002-03-19
申请号：US09596097
申请日：2000-06-16
申请人： Helmut Horst Tews , Jonathan E. Faltermeir , Rajeev Malik , Carol Heenan , Oleg Gluschenkov
发明人： Helmut Horst Tews , Jonathan E. Faltermeir , Rajeev Malik , Carol Heenan , Oleg Gluschenkov
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , C30B29/06 , C30B33/00 , H01L21/02238 , H01L21/02255 , H01L21/02337 , H01L21/28176 , H01L21/28211 , H01L21/31662 , H01L21/76202 , H01L29/513 , H01L29/518 , Y10S438/973
摘要： A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate where silicon surfaces have at least two different crystallographic orientations of the silicon crystal. Atomic oxygen (O) is formed for oxidizing the surfaces. An oxide is formed on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.
摘要翻译：根据本发明，在硅的至少两个结晶平面上形成基本均匀厚度的氧化物的方法包括提供其中硅表面具有硅晶体的至少两个不同晶体取向的衬底。形成氧化表面的原子氧（O）。通过使原子氧与表面反应，在表面上形成氧化物，同时形成表面上氧化物的基本均匀的厚度。

4. 发明授权

US06261972B1 Dual gate oxide process for uniform oxide thickness 有权
标题翻译：双栅氧化法，均匀氧化物厚度
公开(公告)号：US06261972B1
公开(公告)日：2001-07-17
申请号：US09706641
申请日：2000-11-06
申请人： Helmut Horst Tews , Mary Weybright , Stephan Kudelka , Oleg Gluschenkov , Suri Hegde
发明人： Helmut Horst Tews , Mary Weybright , Stephan Kudelka , Oleg Gluschenkov , Suri Hegde
IPC分类号： H01L2100
CPC分类号： H01L21/28185 , H01L21/26506 , H01L21/28202 , H01L21/2822 , H01L21/28238 , H01L21/823462 , H01L27/10873 , H01L29/518 , Y10S438/981
摘要： A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising: a) growing a sacrificial oxide layer on a substrate; b) implanting a dopant through the sacrificial oxide layer; c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface; e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide; f) implanting a second dosage of nitrogen ions through the photoresist; g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.
摘要翻译：一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c）不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以允许氮扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双栅氧化物的薄氧化物的位置; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。

5. 发明申请

US20110278680A1 Strained Semiconductor Device and Method of Making the Same 有权
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US20110278680A1
公开(公告)日：2011-11-17
申请号：US13193692
申请日：2011-07-29
申请人： Helmut Horst Tews , Andre Schenk
发明人： Helmut Horst Tews , Andre Schenk
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L27/1203 , H01L29/66477 , H01L29/6653 , H01L29/66636 , H01L29/7834
摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.
摘要翻译：在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。栅电极与半导体本体电绝缘。沿着栅电极的侧壁形成第一侧壁间隔物。邻近第一侧壁间隔件形成牺牲侧壁间隔物。牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。

6. 发明申请

US20100330771A1 Moisture Barrier Capacitors in Semiconductor Components 审中-公开
标题翻译：半导体元件中的阻水电容器
公开(公告)号：US20100330771A1
公开(公告)日：2010-12-30
申请号：US12876866
申请日：2010-09-07
申请人： Hans-Joachim Barth , Helmut Horst Tews
发明人： Hans-Joachim Barth , Helmut Horst Tews
IPC分类号： H01L21/02
CPC分类号： H01L28/75 , G06F17/5068 , H01L21/76897 , H01L22/14 , H01L23/5223 , H01L23/5226 , H01L23/562 , H01L23/585 , H01L27/0611 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.
摘要翻译：公开了在半导体部件上形成防潮电容器的结构和方法。电容器位于半导体芯片的周围，并且包括电连接到电压节点的内板，具有用于电连接到不同电压节点的翅片的外板。

7. 发明授权

US07157328B2 Selective etching to increase trench surface area 有权
标题翻译：选择性蚀刻以增加沟槽表面积
公开(公告)号：US07157328B2
公开(公告)日：2007-01-02
申请号：US11047312
申请日：2005-01-31
申请人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
发明人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
IPC分类号： H01L21/8242
CPC分类号： H01L21/30604 , H01L29/66181
摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.
摘要翻译：在衬底中形成的沟槽的壁的表面积增加。阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角沟渠墙壁的交叉点。

8. 发明授权

US06967147B1 Nitrogen implantation using a shadow effect to control gate oxide thickness in DRAM semiconductor 失效
标题翻译：使用阴影效应的氮注入来控制DRAM半导体中的栅极氧化物厚度
公开(公告)号：US06967147B1
公开(公告)日：2005-11-22
申请号：US09714356
申请日：2000-11-16
申请人： Helmut Horst Tews , Jochen Beintner
发明人： Helmut Horst Tews , Jochen Beintner
IPC分类号： H01L20060101 , H01L21/265 , H01L21/28 , H01L21/76 , H01L21/8234 , H01L21/8242 , H01L27/06
CPC分类号： H01L21/823462 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/823481 , H01L27/0629 , H01L27/10873 , Y10S438/981
摘要： Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers is used to create a “shadow effect” or area, which limits the nitrogen dose close to the edges of the active area. The reduction of nitrogen dose leads to an increased gate oxide thickness at the active area (AA) adjacent to the shallow trench, increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.
摘要翻译：用于通过使用氮注入并入不同厚度的栅极氧化物来形成用于DRAMS的双栅极氧化物的工艺。使用倾斜的氮气注入或氮化物间隔物来产生“阴影效应”或区域，这限制了接近有效区域边缘的氮剂量。氮剂量的减少导致在与浅沟槽相邻的有源区（AA）处的栅极氧化物厚度增加，增加了寄生角装置的阈值并且减小了副Vt（阈值电压）和结漏电。

9. 发明授权

US06677197B2 High aspect ratio PBL SiN barrier formation 有权
标题翻译：高纵横比PBL SiN阻挡层形成
公开(公告)号：US06677197B2
公开(公告)日：2004-01-13
申请号：US10032040
申请日：2001-12-31
申请人： Stephan Kudelka , Helmut Horst Tews
发明人： Stephan Kudelka , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L29/66181
摘要： In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.
摘要翻译：在制备通常需要在瓶形成后形成套环的亚100nm研磨剂制备DT DRAM的方法中，通过形成高面积比PBL SiN阻挡层来改进提供轴环第一方案，该方法包括：a）在SiN结点沉积和DT多晶硅填充之后的半导体结构; b）沉积多层缓冲LOCOS（PBL）Si衬垫; c）使PBL衬里氧化形成衬垫氧化物并沉积SiN阻挡层; d）沉积硅掩模衬垫; e）使用p-掺杂剂对DT进行高定向离子注入（I / I）; f）使用SiN上的蚀刻停止对未被注入的Si的选择性湿蚀刻; g）使步骤f）的产物在衬垫氧化物上具有蚀刻停止层的SiN湿蚀刻; h）影响衬垫氧化物上的停止的Si衬层蚀刻; i）氧化PBL Si衬垫并影响势垒SiN条; j）提供DT多晶硅填充物进行多化学机械抛光。

10. 发明授权

US08569820B2 Capacitor having a plurality of parallel conductive members 有权
标题翻译：具有多个平行导电构件的电容器
公开(公告)号：US08569820B2
公开(公告)日：2013-10-29
申请号：US13344714
申请日：2012-01-06
申请人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
发明人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
IPC分类号： H01L27/108
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

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