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11. 发明授权

US6060369A Nitrogen bearing sacrificial oxide with subsequent high nitrogen dopant profile for high performance MOSFET 失效
标题翻译：含氮牺牲氧化物，具有高性能MOSFET的高氮掺杂剂分布
公开(公告)号：US6060369A
公开(公告)日：2000-05-09
申请号：US997318
申请日：1997-12-23
申请人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford
发明人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L21/823807
摘要： A integrated circuit transistor that has a high nitrogen concentration in the channel region and a method of making same are provided. A sacrificial oxide layer integrated with a nitrogen bearing species is grown on the substrate. A portion of the nitrogen bearing species diffuses into the substrate to form a nitrogen doped region. Nitrogen is implanted through the first oxide layer to increase the peak concentration of nitrogen in the nitrogen doped region. The sacrificial oxide layer is removed and a very thin gate oxide layer is formed. A gate, a source, and a drain are formed. The result is an integrated circuit transistor with a very thin gate oxide layer and a high peak concentration of nitrogen substantially at the Si--SiO.sub.2 interface.
摘要翻译：提供在通道区域中具有高氮浓度的集成电路晶体管及其制造方法。在基材上生长与含氮物质结合的牺牲氧化物层。含氮物质的一部分扩散到衬底中以形成氮掺杂区域。通过第一氧化物层注入氮气以增加氮掺杂区域中氮的峰值浓度。去除牺牲氧化物层并形成非常薄的栅极氧化物层。形成栅极，源极和漏极。结果是具有非常薄的栅极氧化物层和基本上在Si-SiO 2界面处的高的峰值浓度的集成电路晶体管。

12. 发明授权

US06018180A Transistor formation with LI overetch immunity 失效
标题翻译：晶体管形成与LI过滤免疫
公开(公告)号：US06018180A
公开(公告)日：2000-01-25
申请号：US996648
申请日：1997-12-23
申请人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
发明人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/762 , H01L21/768 , H01L29/76
CPC分类号： H01L21/76895 , H01L21/76224
摘要： An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.
摘要翻译：提供一种集成电路晶体管及其制造方法。晶体管由于局部互连沟槽的过蚀刻而抵抗结短路。该晶体管包括具有第一结的源极/漏极区域和位于有源区域的易于经过过渡接合短路现象的部分中比第一结点更深的第二结点。第二结通过通过掩模的离子注入建立，其被图案化以产生对应于有源区和局部互连沟槽的布局的交点的开口。使用该方法，仅在需要防止短路并且不妨碍晶体管性能的情况下才建立第二结。

13. 发明授权

US06245649B1 Method for forming a retrograde impurity profile 有权
标题翻译：形成逆行杂质分布的方法
公开(公告)号：US06245649B1
公开(公告)日：2001-06-12
申请号：US09251923
申请日：1999-02-17
申请人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
发明人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L2104
CPC分类号： H01L29/105 , H01L21/2652
摘要： A method for forming a retrograde impurity profile in a semiconducting substrate is provided. The method comprises forming a sacrificial layer having a thickness in the range of about 10 Å to about 150 Å on the surface of a semiconducting substrate. Thereafter, an ion implantation process is performed wherein dopant impurity ions are directed through the sacrificial layer and into the semiconducting substrate under conditions effective to form a retrograde impurity profile in the semiconducting substrate.
摘要翻译：提供了一种在半导体衬底中形成逆向杂质分布的方法。该方法包括在半导体衬底的表面上形成具有在大约至大约的范围内的厚度的牺牲层。此后，进行离子注入工艺，其中掺杂杂质离子在有效地在半导体衬底中形成逆向杂质分布的条件下引导通过牺牲层并进入半导体衬底。

14. 发明授权

US06225188B1 Self aligned method for differential oxidation rate at shallow trench isolation edge 有权
标题翻译：浅沟槽隔离边缘微分氧化率自对准方法
公开(公告)号：US06225188B1
公开(公告)日：2001-05-01
申请号：US09524447
申请日：2000-03-14
申请人： Derick J. Wristers , H. Jim Fulford , Mark I. Gardner
发明人： Derick J. Wristers , H. Jim Fulford , Mark I. Gardner
IPC分类号： H01L21265
CPC分类号： H01L21/76237
摘要： A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the portions relative proximal to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.
摘要翻译：提供其中在半导体衬底中形成至少一个隔离结构的半导体工艺。氧离子种类被引入半导体衬底的靠近隔离结构的部分，优选通过使用离子注入到倾斜或倾斜的衬底中。然后在半导体衬底的上表面上形成栅介质层。在半导体衬底的近端部分存在含氧物质增加了部分相对于离开隔离结构远端的部分氧化速率的氧化速率。以这种方式，在半导体衬底的近端部分上的栅极电介质的第一厚度大于半导体衬底的剩余部分上的栅极氧化物层的第二厚度。与隔离沟槽的不连续性相邻的增加的氧化物厚度减小了跨过氧化物的电场。

15. 发明授权

US6103559A Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication 有权
标题翻译：为源/漏和LDD注入和随后的栅极制造做一次性通道掩蔽的方法
公开(公告)号：US6103559A
公开(公告)日：2000-08-15
申请号：US282033
申请日：1999-03-30
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L21/822 , H01L21/8238 , H01L27/06 , H01L29/51 , H01L21/338 , H01L21/3205
CPC分类号： H01L21/28194 , H01L21/28052 , H01L21/28123 , H01L21/8221 , H01L21/823814 , H01L21/823828 , H01L27/0688 , H01L29/517 , H01L29/6659 , H01L21/28202 , H01L29/518 , H01L29/66545
摘要： A method is provided for fabricating a semiconductor device, the method including forming a first dielectric layer above a structure and forming an island of a sacrificial layer above the first dielectric layer. The method also includes introducing a first dopant into first portions of the structure, leaving a second portion of the structure protected by the island, and removing first portions of the island leaving a second portion of the island. The method further includes introducing a second dopant into the first portions and third portions of the structure, leaving a fourth portion of the structure protected by the second portion of the island. The method additionally includes forming a second dielectric layer adjacent the second portion of the island, removing the second portion of the island, forming a gate dielectric above the fourth portion of the structure and forming a gate conductor above the gate dielectric.
摘要翻译：提供了一种用于制造半导体器件的方法，所述方法包括在结构之上形成第一介电层，并在第一介电层上形成牺牲层的岛。该方法还包括将第一掺杂剂引入到结构的第一部分中，留下由岛保护的结构的第二部分，以及去除离开岛的第二部分的岛的第一部分。该方法还包括将第二掺杂剂引入到结构的第一部分和第三部分中，留下结构的第四部分被岛的第二部分保护。该方法还包括形成与岛的第二部分相邻的第二电介质层，去除岛的第二部分，在结构的第四部分之上形成栅极电介质，并在栅极电介质上方形成栅极导体。

16. 发明授权

US5904534A Transistor formation with local interconnect overetch immunity 有权
标题翻译：晶体管形成与局部互连overetch免疫
公开(公告)号：US5904534A
公开(公告)日：1999-05-18
申请号：US134702
申请日：1998-08-14
申请人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
发明人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/762 , H01L21/768 , H01L21/336 , H01L21/76
CPC分类号： H01L21/76895 , H01L21/76224
摘要： An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.
摘要翻译：提供一种集成电路晶体管及其制造方法。晶体管由于局部互连沟槽的过蚀刻而抵抗结短路。该晶体管包括具有第一结的源极/漏极区域和位于有源区域的易于经过过渡接合短路现象的部分中比第一结点更深的第二结点。第二结通过通过掩模的离子注入建立，其被图案化以产生对应于有源区和局部互连沟槽的布局的相交的开口。使用该方法，仅在需要防止短路并且不妨碍晶体管性能的情况下才建立第二结。

17. 发明授权

US5891787A Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure 失效
标题翻译：半导体制造采用在沟槽隔离结构的边缘处植入多余的原子
公开(公告)号：US5891787A
公开(公告)日：1999-04-06
申请号：US923181
申请日：1997-09-04
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 .ANG.. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted into regions of the active areas in close proximity to the trench isolation structure.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在半导体衬底上形成电介质掩模层。然后通过掩模层形成开口。在开口内的掩模层的侧壁上形成一对电介质隔离物。然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。然后在沟槽的壁和基底上热生长第一介电层。将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。间隔物的部分也被去除，使得间隔物的厚度在约0至200安培之间。然后将硅原子和/或势垒原子（例如氮原子）注入紧邻沟槽隔离结构的有源区的区域中。

18. 发明授权

US06180475B2 Transistor formation with local interconnect overetch immunity 有权
标题翻译：晶体管形成与局部互连overetch免疫
公开(公告)号：US06180475B2
公开(公告)日：2001-01-30
申请号：US09134702
申请日：1998-08-14
申请人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
发明人： Jon D. Cheek , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21336
CPC分类号： H01L21/76895 , H01L21/76224
摘要： An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.
摘要翻译：提供一种集成电路晶体管及其制造方法。晶体管由于局部互连沟槽的过蚀刻而抵抗结短路。该晶体管包括具有第一结的源极/漏极区域和位于有源区域的易于经过过渡接合短路现象的部分中比第一结点更深的第二结点。第二结通过通过掩模的离子注入建立，其被图案化以产生对应于有源区和局部互连沟槽的布局的相交的开口。使用该方法，仅在需要防止短路并且不妨碍晶体管性能的情况下才建立第二结。

19. 发明授权

US6097062A Optimized trench edge formation integrated with high quality gate formation 失效
标题翻译：优化的沟槽边缘形成集成了高质量的栅极形成
公开(公告)号：US6097062A
公开(公告)日：2000-08-01
申请号：US928821
申请日：1997-09-12
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/265 , H01L21/266 , H01L21/28 , H01L21/32 , H01L21/762 , H01L29/423 , H01L29/72
CPC分类号： H01L21/28211 , H01L21/26506 , H01L21/266 , H01L21/32 , H01L21/76213 , H01L21/76224 , H01L29/42368
摘要： A semiconductor manufacturing process is provided in which an oxidation retarding species is introduced into regions of the substrate distal from the isolation structures. A subsequent thermal oxidation process results in the formation of a gate dielectric film in which the film thickness proximal to the isolation structures is greater than the film thickness distal from the isolation structures. Broadly speaking, an isolation structure is formed in an isolation region of a semiconductor substrate. A mask is then formed on an upper surface of the semiconductor substrate. The mask covers the isolation structure and portions of the semiconductor substrate proximal to the isolation structure. A nitrogen bearing impurity distribution is then introduced into portions of the semiconductor substrate exposed by the mask. The nitrogen bearing impurity distribution therefore substantially resides within portions of the semiconductor substrate distal from the isolation structures. A gate dielectric is then formed on an upper surface of the semiconductor substrate. An oxidation rate of the distal portions of the semiconductor substrate is less than an oxidation rate of the proximal portions. In this manner, a thickness of the gate oxide is greater over the proximal portions of the substrate than over the distal portions.
摘要翻译：提供半导体制造方法，其中将氧化延迟物质引入到远离隔离结构的衬底的区域中。随后的热氧化过程导致栅极电介质膜的形成，其中靠近隔离结构的膜厚度大于远离隔离结构的膜厚度。广义地说，在半导体衬底的隔离区域中形成隔离结构。然后在半导体衬底的上表面上形成掩模。掩模覆盖隔离结构和靠近隔离结构的半导体衬底的部分。然后将含氮杂质分布引入由掩模曝光的半导体衬底的部分中。因此，含氮杂质分布基本上位于远离隔离结构的半导体衬底的部分内。然后在半导体衬底的上表面上形成栅极电介质。半导体衬底的远端部分的氧化速度小于近端部分的氧化速率。以这种方式，栅极氧化物的厚度比基底的近端部分大得多。

20. 发明授权

US5976924A Method of making a self-aligned disposable gate electrode for advanced CMOS design 失效
标题翻译：制造用于先进CMOS设计的自对准一次性栅电极的方法
公开(公告)号：US5976924A
公开(公告)日：1999-11-02
申请号：US599
申请日：1997-12-30
申请人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford
发明人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L29/66575 , H01L29/66545
摘要： A method of fabricating an integrated circuit transistor in a substrate is provided wherein a self-aligned gate electrode is formed after the high temperature steps associated with sidewall spacer formation and source/drain anneal. A first dielectric layer is formed on a substrate. First and second source/drain regions are formed in the substrate and spaced laterally to define a channel region underlying the first dielectric layer. A second dielectric layer is formed on the substrate except where the first dielectric layer is positioned. The first dielectric layer is removed and a third dielectric layer is formed that overlies the channel region. A gate electrode is formed on the third dielectric layer. The first dielectric layer functions as a disposable gate electrode to facilitate self-aligned source/drain implant and sidewall spacer formation.
摘要翻译：提供一种在衬底中制造集成电路晶体管的方法，其中在与侧壁间隔物形成和源/漏退火相关联的高温步骤之后形成自对准栅电极。在基板上形成第一电介质层。第一和第二源极/漏极区域形成在衬底中并且横向隔开以限定第一电介质层下面的沟道区域。第二电介质层形成在基板上，除了第一介电层被定位之外。去除第一介电层，并形成覆盖沟道区的第三介电层。栅电极形成在第三电介质层上。第一介电层用作一次性栅电极，以促进自对准的源极/漏极注入和侧壁间隔物的形成。

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