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11. 发明授权

US06988173B2 Bus protocol for a switchless distributed shared memory computer system 失效
标题翻译：总线协议用于无交换分布式共享内存计算机系统
公开(公告)号：US06988173B2
公开(公告)日：2006-01-17
申请号：US10435878
申请日：2003-05-12
申请人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
发明人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system. The bus protocol also allows data to be returned on one of the two rings, with the ring selection determined by the relative placement of the source and destination nodes on each ring, in order to control latency and data bus utilization.
摘要翻译：公开了一种用于由多个节点组成的对称多处理计算机系统的总线协议，每个节点包含多个处理器，I / O设备，主存储器和包括具有顶级高速缓存的集成交换机的系统控制器。节点通过双同心环拓扑互连。总线协议用于以一种允许部分一致性结果与窥探请求和地址并行传送的方式来交换窥探请求和地址，数据，相关性信息和节点之间的操作状态，因为操作沿着每个环转发。每个节点将其自身的一致性结果与在将窥探请求转发之前接收的部分一致性结果相结合，将地址和更新的部分一致性结果合并到环上的下一个节点。该协议允许系统中的每个节点查看最终的一致性结果，而不需要请求节点将这些结果广播到系统中的所有其他节点。总线协议还允许在两个振铃中的一个上返回数据，其中环选择由每个振铃上的源节点和目的节点的相对位置确定，以便控制等待时间和数据总线的利用。

12. 发明授权

US6151655A Computer system deadlock request resolution using timed pulses 失效
标题翻译：使用定时脉冲的计算机系统死锁请求分辨率
公开(公告)号：US6151655A
公开(公告)日：2000-11-21
申请号：US70432
申请日：1998-04-30
申请人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
发明人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
IPC分类号： G06F15/177 , G06F9/46 , G06F9/52 , G06F12/00
CPC分类号： G06F9/524
摘要： Disclosed is a hardware mechanism for detecting and avoiding potential deadlocks among requestors in a multiprocessor system, consisting of a plurality of CP's and I/O adapters connected to one or more shared storage controllers (SC's). Requests to each storage controller originate from external sources such as the CP's, the I/O adapters, and the other SC, as well as from internal sources, such as the hardware facilities used to process fetches and stores between the SC and main memory. All requests must be granted priority before beginning to execute, using a ranked priority order scheme. Specific sequences of requests may cause deadlocks, either due to high-priority requests using priority cycles and locking out low-priority requests, or as a result of requests of any priority level busying resources needed for the completion of other requests. The deadlock resolution mechanism described here monitors the length of time a request has been valid in the storage controller without completing, by checking the request register valid bits and utilizing a timed pulse, which is a subset of the pulse used to detect hangs within the SC. If the valid bit for a request register is on, and two timed pulses are received, an internal hang detect latch is set. If the valid bit is reset at any time, the detection logic and the internal hang detect latch are reset. When the internal hang detect latch is set, requests in progress are allowed to complete, and new requests are held in an inactive state, until the request which detected the internal hang is able to complete.
摘要翻译：公开了一种用于检测和避免多处理器系统中的请求者之间潜在的死锁的硬件机制，其由连接到一个或多个共享存储控制器（SC）的多个CP和I / O适配器组成。对每个存储控制器的请求源自诸如CP，I / O适配器和其他SC的外部源，以及来自内部源（例如用于处理SC和主存储器之间的获取和存储的硬件设施）。所有请求必须在开始执行之前被赋予优先级，使用排名优先顺序方案。特定的请求序列可能会由于高优先权请求使用优先级周期和锁定低优先级请求而导致死锁，或者由于完成其他请求所需的任何优先级级别的资源请求而产生死锁。这里描述的死锁解析机制通过检查请求寄存器有效位并利用定时脉冲来监视存储控制器中的请求已经有效的时间长度，并且使用定时脉冲，定时脉冲是用于检测SC内的挂起的脉冲的子集。如果请求寄存器的有效位为开，并且接收到两个定时脉冲，则设置内部挂起检测锁存器。如果有效位在任何时候被复位，则检测逻辑和内部挂起检测锁存器被复位。当设置内部挂起检测锁存器时，允许正在进行的请求完成，并且新的请求保持在非活动状态，直到检测到内部挂起的请求能够完成为止。

13. 发明授权

US6073182A Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic 失效
标题翻译：使用全局挂起脉冲逻辑解决多处理器中竞争请求之间的死锁的方法
公开(公告)号：US6073182A
公开(公告)日：2000-06-06
申请号：US70664
申请日：1998-04-30
申请人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
发明人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
IPC分类号： G06F13/16 , G06F15/16 , G06F15/173
CPC分类号： G06F13/1663
摘要： A method using a global hang pulse logic mechanism detects and resolves deadlocks among requesters to the storage controller of a symmetric multiprocessor system in which multiple central processors and I/O adapters are connected to one or more shared storage controllers. Deadlocks may occur in such a system due to specific sequences of requests, either because high priority requests use priority cycles and lock out low priority requests, or because requests of any priority level make resources needed for the completion of other requests too busy. The mechanism logic monitors the length of time a request has been valid in the storage controller without completing, by checking the request register valid bits, and by utilizing a timed pulse which is a subset of the pulse used to detect hangs within the storage controller. If the valid bit is reset at any time detection logic and an internal hang detect latch is set, Logic which allows requests in progress to complete, and holds new requests in an inactive state is activated when the internal hang latch is set and remains active until the request which detected the internal hang is able to complete, thus resetting the internal hang detect latch.
摘要翻译：使用全局挂起脉冲逻辑机制的方法检测并解决请求者之间的死锁到其中多个中央处理器和I / O适配器连接到一个或多个共享存储控制器的对称多处理器系统的存储控制器。由于高优先级请求使用优先级周期并锁定低优先级请求，或者由于任何优先级的请求使得完成其他请求太繁忙所需的资源，因此在这种系统中可能会由于特定的请求序列而在这样的系统中发生死锁。机制逻辑监视存储控制器中的请求已经有效的时间长度，而不需要通过检查请求寄存器有效位以及利用作为用于检测存储控制器内的挂起的脉冲的子集的定时脉冲来完成。如果有效位在任何时候被复位，则检测逻辑和内部挂起检测锁存器被置位，当内部挂起锁存器被设置并且保持有效时，激活允许正在进行中的请求完成并保持处于非活动状态的新请求的逻辑，直到检测到内部挂起的请求能够完成，从而重置内部挂起检测锁存器。

14. 发明授权

US08918587B2 Multilevel cache hierarchy for finding a cache line on a remote node 有权
标题翻译：用于在远程节点上查找缓存行的多级缓存层次结构
公开(公告)号：US08918587B2
公开(公告)日：2014-12-23
申请号：US13495373
申请日：2012-06-13
申请人： Timothy C. Bronson , Garrett M. Drapala , Michael A. Blake , Craig R. Walters , Pak-Kin Mak
发明人： Timothy C. Bronson , Garrett M. Drapala , Michael A. Blake , Craig R. Walters , Pak-Kin Mak
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0884 , G06F12/123
摘要： Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.
摘要翻译：实施例涉及在具有系统存储器的多级缓存系统上访问高速缓存行。基于本地节点对特定高速缓存线的独占所有权的请求，请求被本地节点同时发送到用于特定高速缓存行的多个节点的系统内存和远程节点。在特定的远程节点中找到特定的高速缓存行。特定的远程节点是远程节点之一。从特定的远程节点中删除特定的高速缓存行以供另一个节点独占所有。基于具有指定缓存行在幽灵状态的指定节点，任何后续的提取请求将针对具体的缓存行启动，特定的缓存行遇到幽灵状态。当遇到鬼状态时，后续的提取请求仅被引导到多个节点的节点。

15. 发明申请

US20110320755A1 TRACKING DYNAMIC MEMORY REALLOCATION USING A SINGLE STORAGE ADDRESS CONFIGURATION TABLE 失效
标题翻译：使用单个存储地址配置表跟踪动态内存重新安装
公开(公告)号：US20110320755A1
公开(公告)日：2011-12-29
申请号：US12821986
申请日：2010-06-23
申请人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
发明人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
IPC分类号： G06F12/06
CPC分类号： G06F12/0292
摘要： Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.
摘要翻译：使用具有第一寄存器和第二寄存器的单个配置表来跟踪动态存储器去分配包括将第一寄存器设置为活动寄存器，启动从存储器分区的期望存储增量的去分配，在第二寄存器中设置存储增量注册为无效，清除与单个配置表相关联的所有高速缓存，将第二个寄存器设置为活动寄存器，将第一个寄存器设置为非活动寄存器，将第一个寄存器中的所需存储增量设置为无效，将活动寄存器从第二个注册到第一个寄存器，使用单个配置表完成内存取消分配。

16. 发明申请

US20110314228A1 Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer 失效
标题翻译：维持多节点对称多处理计算机中的缓存一致性
公开(公告)号：US20110314228A1
公开(公告)日：2011-12-22
申请号：US12816464
申请日：2010-06-16
申请人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0833
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译：在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由第一计算节点对高速缓存未命中的高速缓存行的请求进行广播; 从每个其他计算节点向所有其他节点传送该节点上的高速缓存行的状态，包括从具有正确副本的任何计算节点向第一节点发送正确的高速缓存行副本; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。

17. 发明申请

US20090210629A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SELECTIVELY PURGING CACHE ENTRIES 审中-公开
标题翻译：方法，系统和计算机程序产品，用于选择高速缓存进入
公开(公告)号：US20090210629A1
公开(公告)日：2009-08-20
申请号：US12032058
申请日：2008-02-15
申请人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
发明人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A method, system and computer program product for selectively purging entries in a cache of a computer system. The method includes determining a starting storage address and a length of the storage address range to be purged, determining preset values for a congruence class and a compartment of a cache directory, accessing the cache directory based on the preset value of the congruence class, and selecting an entry in the cache directory based on the preset value of the compartment, determining validity of the entry accessed by examining an ownership tag of the entry, comparing a line address of the entry with the starting storage address and a sum of the starting storage address and the length of the storage address range, and selectively purging the entry based on the comparison result.
摘要翻译：一种用于选择性地清除计算机系统的高速缓存中的条目的方法，系统和计算机程序产品。该方法包括确定要清除的存储地址范围的起始存储地址和长度，确定高速缓存目录的同余类和隔间的预设值，基于同余类的预设值访问高速缓存目录;以及基于所述隔室的所述预设值来选择所述缓存目录中的条目，通过检查所述条目的所有权标签来确定所访问的条目的有效性，将所述条目的行地址与所述起始存储地址进行比较，以及所述起始存储器地址和存储地址范围的长度，并且基于比较结果选择性地清除条目。

18. 发明申请

US20080071990A1 Method for Ensuring Fairness Among Requests Within a Multi-Node Computer System 有权
标题翻译：确保多节点计算机系统内的请求之间公平的方法
公开(公告)号：US20080071990A1
公开(公告)日：2008-03-20
申请号：US11532156
申请日：2006-09-15
申请人： Craig R Walters , Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak
发明人： Craig R Walters , Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0815
摘要： A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed successfully. By providing the alternate valid bits the dual set of resource valids for each remote requester is provided for each remote requester, where one set of valids indicates if the resource is valid and actively working on the line, and the other set of valids indicates if the resource was valid but encountered some conflict that requires resolution before the request can complete. Only on successful reload and completion of the remote operation does this alternate address valid bit reset and open the way for any pending interface requests to proceed, so all outstanding requests currently loaded in a local resource within the nest system are able to complete before new interface requests are allowed into the system.
摘要翻译：使用包括常规位集合和备用有效位集合的双重有效位集合的方法，其阻止对给定高速缓存行的新请求进入多节点计算机系统的嵌套系统，直到对给定高速缓存行的所有请求已经完成为止成功了通过提供替代的有效位，为每个远程请求者提供用于每个远程请求者的两组资源代码，其中一组代码指示资源是否有效并且在该行上主动地工作，而另一组代码指示是否资源有效，但在请求完成之前遇到一些需要解决的冲突。只有在成功重新加载和完成远程操作时，这个备用地址有效位复位，并为任何待处理的接口请求继续进行打开方式，因此当前加载到嵌套系统中的本地资源的所有未完成的请求都可以在新界面之前完成请求被允许进入系统。

19. 发明授权

US07085898B2 Coherency management for a “switchless” distributed shared memory computer system 失效
标题翻译： “无切换”分布式共享内存计算机系统的一致性管理
公开(公告)号：US07085898B2
公开(公告)日：2006-08-01
申请号：US10435776
申请日：2003-05-12
申请人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
发明人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
IPC分类号： G06F12/00 , G06F15/167 , H04L12/43
CPC分类号： G06F12/0813 , G06F12/0831
摘要： An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are launched onto the ring topology simultaneously in both directions. As the messages traverse the nodes on the ring, they trigger remote controllers to perform coherent actions such as cache accesses or directory updates. Messages arriving on each node from both directions are combined with each other and with locally generated responses to form cumulative final responses. Additionally, controllers on the requesting node may perform local coherent actions based on the information conveyed by the returning final responses. Overall system coherency is maintained through the use of a dual token based scheme which provide coherency points to permit multiple non-contending requests for the same data unit. The cache coherency methods described herein further ensure the latest copy of data is always accessed or modified even when multiple copies are present throughout the multi-nodal system structure. Traditional cache management states are extended to include Intervention Master and Multiple Copy status which minimize overall bus utilization. A novel ring protocol is contemplated which efficiently packages coherency information into bus operational responses that also allow simultaneous data transfers in the direction of minimal latency.
摘要翻译：公开了一种用于管理具有多个节点的对称多处理环境中的存储一致性的装置和方法，每个节点包含多个处理器，I / O适配器，主存储器和包括具有顶级缓存的集成开关的系统控制器。节点通过双同心环拓扑互连。任何给定节点上的本地控制器代表该节点上的所述处理器和I / O适配器启动总线操作。 Snoop请求在两个方向同时发送到环形拓扑上。当消息遍历环上的节点时，它们触发远程控制器执行诸如缓存访问或目录更新之类的一致操作。从两个方向到达每个节点的消息彼此组合并且具有本地生成的响应以形成累积的最终响应。此外，请求节点上的控制器可以基于返回的最终响应传达的信息来执行本地一致的动作。通过使用基于双令牌的方案来维护总体系统一致性，其提供相干点以允许对相同数据单元的多个非竞争请求。本文所述的高速缓存一致性方法进一步确保即使在整个多节点系统结构中存在多个副本，始终访问或修改数据的最新副本。传统的缓存管理状态被扩展到包括干预主机和复制状态，从而最大限度地减少总线总线利用率。考虑了一种新颖的环路协议，其有效地将一致性信息包装到总线操作响应中，其也允许以最小延迟的方向同时进行数据传输。

20. 发明授权

US07818504B2 Storage system that prioritizes storage requests 失效
标题翻译：存储系统优先处理存储请求
公开(公告)号：US07818504B2
公开(公告)日：2010-10-19
申请号：US11861765
申请日：2007-09-26
申请人： Derrin M. Berger , Michael A. Blake , Garrett M Drapala , Pak-kin Mak
发明人： Derrin M. Berger , Michael A. Blake , Garrett M Drapala , Pak-kin Mak
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0851 , G06F12/0855
摘要： A storage system may include storage, a main pipeline to carry data for the storage, and a store pipeline to carry data for the storage. The storage system may also include a controller to prioritize data storage requests for the storage based upon available interleaves and which pipeline is associated with the data storage requests.
摘要翻译：存储系统可以包括存储器，用于存储用于存储数据的主流水线以及用于存储数据的存储流水线。存储系统还可以包括控制器，用于基于可用的交织以及哪个流水线与数据存储请求相关联地对存储的数据存储请求进行优先级排序。

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