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1. 发明申请

US20110320665A1 Managing Concurrent Serialized Interrupt Broadcast Commands In A Multi-Node, Symmetric Multiprocessing Computer 失效
标题翻译：在多节点对称多处理计算机中管理并发序列化中断广播命令
公开(公告)号：US20110320665A1
公开(公告)日：2011-12-29
申请号：US12821752
申请日：2010-06-23
申请人： Garrett M. Drapala , Christine C. Jones , Pak-Kin Mak , Craig R. Walters
发明人： Garrett M. Drapala , Christine C. Jones , Pak-Kin Mak , Craig R. Walters
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of serialized interrupt broadcast commands; receiving, by the communications adapter, a plurality of interrupt tags for the plurality of serialized interrupt broadcast commands, each interrupt tag including an identification of an interrupt service order for a serialized interrupt broadcast command; assigning, by the communications adapter, to each serialized interrupt broadcast command its interrupt tag; and if an interrupt tag assigned to a serialized interrupt broadcast command has an interrupt service order that matches a value of a current operation tag that identifies the next serialized interrupt broadcast command to be exposed to the one or more processors, exposing, by the communications adapter, the serialized interrupt broadcast command to the one or more processors on the compute node to be serviced.
摘要翻译：在多节点对称多处理计算机中管理并发的串行化中断广播命令，包括由计算节点中的通信适配器接收多个串行化的中断广播命令; 由通信适配器接收多个串行化中断广播命令的多个中断标签，每个中断标签包括用于串行化中断广播命令的中断服务命令的标识; 由通信适配器将每个序列化的中断广播命令分配给其中断标签; 并且如果分配给序列化中断广播命令的中断标签具有与当前操作标签的值相匹配的中断服务订单，该当前操作标签的值标识要暴露给所述一个或多个处理器的下一个串行化中断广播命令，则由通信适配器将序列化的中断广播命令发送到要被服务的计算节点上的一个或多个处理器。

2. 发明授权

US07779189B2 Method, system, and computer program product for pipeline arbitration 失效
标题翻译：管道仲裁的方法，系统和计算机程序产品
公开(公告)号：US07779189B2
公开(公告)日：2010-08-17
申请号：US12035249
申请日：2008-02-21
申请人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
发明人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
IPC分类号： G06F13/36 , G06F12/00 , G06F13/00 , H03M13/00
CPC分类号： G06F13/36
摘要： A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.
摘要翻译：一种用于流水线仲裁的方法，包括从第一流水线接收对共享芯片接口的第一请求，确定第一请求是否需要共享芯片接口的响应总线，以及如果确定不需要响应总线第一请求，认为第一请求仅需要共享芯片接口的地址总线，对从第二管道接收的用于访问地址总线的共享芯片接口的第二请求仲裁第一请求，将第一请求发送到所述地址总线如果所述第一请求通过所述第二请求获胜所述仲裁，并且如果所述第二请求通过所述第一请求获胜仲裁，则拒绝所述第一请求。相应的系统和计算机程序产品。

3. 发明申请

US20090216933A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PIPELINE ARBITRATION 失效
标题翻译：用于管道仲裁的方法，系统和计算机程序产品
公开(公告)号：US20090216933A1
公开(公告)日：2009-08-27
申请号：US12035249
申请日：2008-02-21
申请人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
发明人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.
摘要翻译：一种用于流水线仲裁的方法，包括从第一流水线接收对共享芯片接口的第一请求，确定第一请求是否需要共享芯片接口的响应总线，以及如果确定不需要响应总线第一请求，认为第一请求仅需要共享芯片接口的地址总线，对从第二管道接收的用于访问地址总线的共享芯片接口的第二请求仲裁第一请求，将第一请求发送到所述地址总线如果所述第一请求通过所述第二请求获胜所述仲裁，并且如果所述第二请求通过所述第一请求获胜仲裁，则拒绝所述第一请求。相应的系统和计算机程序产品。

4. 发明申请

US20090193194A1 Method for Expediting Return of Line Exclusivity to a Given Processor in a Symmetric Multiprocessing Data Processing System 失效
标题翻译：在对称多处理数据处理系统中加速返回给定处理器的排除独占性的方法
公开(公告)号：US20090193194A1
公开(公告)日：2009-07-30
申请号：US12021403
申请日：2008-01-29
申请人： Garrett M. Drapala , Pak-kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Garrett M. Drapala , Pak-kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A method and apparatus for eliminating, in a multi-nodes data handling system, contention for exclusivity of lines in cache memory through improved management of system buses, processor cross-invalidate stacks, and the system operations that can lead to these requested cache operations being rejected.
摘要翻译：一种用于在多节点数据处理系统中消除通过改进的系统总线管理，处理器交叉无效堆栈以及可导致这些所请求的高速缓存操作的系统操作的高速缓冲存储器中线路排他性的争用的方法和装置拒绝。

5. 发明授权

US06462665B1 Method and apparatus for sending a weather condition alert 有权
标题翻译：用于发送天气状况警报的方法和装置
公开(公告)号：US06462665B1
公开(公告)日：2002-10-08
申请号：US09571447
申请日：2000-05-16
申请人： Peter B. Tarlton , Daniel P. Millerick , Craig R. Walters
发明人： Peter B. Tarlton , Daniel P. Millerick , Craig R. Walters
IPC分类号： G01W100
CPC分类号： G08B21/10 , G01W1/02
摘要： A method and apparatus of an alert system for notifying subscribers of weather or hazardous conditions. A weather-tracking source or service broadcasts weather or hazardous conditions across the nation to alert the general public of potentially dangerous climatic and hazardous conditions that may arise from time to time. A weather service provider receives the weather condition broadcasts from the weather-tracking source or service and transmits weather or hazardous condition signals to subscribers having an alert unit. The alert unit is a passive device capable of receiving and warning the subscribers of the weather or hazardous condition broadcasts.
摘要翻译：一种警报系统的方法和装置，用于通知用户天气或危险状况。天气跟踪来源或服务广播全国各地的天气或危险情况，以警惕公众不时可能出现的潜在危险的气候和危险状况。天气服务提供商从天气跟踪源或服务器接收天气状况广播，并向具有警报单元的用户发送天气或危险状况信号。警报单元是能够接收和警告用户天气或危险状况广播的被动设备。

6. 发明授权

US09558119B2 Main memory operations in a symmetric multiprocessing computer 有权
标题翻译：对称多处理计算机中的主存储器操作
公开(公告)号：US09558119B2
公开(公告)日：2017-01-31
申请号：US12821540
申请日：2010-06-23
申请人： Garrett M. Drapala , Pak-Kin Mak , Arthur J. O'Neill, Jr. , Craig R. Walters
发明人： Garrett M. Drapala , Pak-Kin Mak , Arthur J. O'Neill, Jr. , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0831
摘要： Main memory operation in a symmetric multiprocessing computer, the computer comprising one or more processors operatively coupled through a cache controller to at least one cache of main memory, the main memory shared among the processors, the computer further comprising input/output (‘I/O’) resources, including receiving, in the cache controller from an issuing resource, a memory instruction for a memory address, the memory instruction requiring writing data to main memory; locking by the cache controller the memory address against further memory operations for the memory address; advising the issuing resource of completion of the memory instruction before the memory instruction completes in main memory; issuing by the cache controller the memory instruction to main memory; and unlocking the memory address only after completion of the memory instruction in main memory.
摘要翻译：在对称多处理计算机中的主存储器操作，所述计算机包括通过高速缓存控制器操作地耦合到主存储器的至少一个高速缓存的一个或多个处理器，所述主存储器在所述处理器之间共享，所述计算机还包括输入/输出（“I / O'）资源，包括从发行资源在高速缓存控制器中接收存储器地址的存储器指令，需要向主存储器写入数据的存储器指令; 由缓存控制器锁定存储器地址，以防止存储器地址的进一步存储器操作; 在存储器指令在主存储器中完成之前建议完成存储器指令的发布资源; 由缓存控制器发出存储器指令给主存储器; 并且仅在主存储器中的存储器指令完成之后解锁存储器地址。

7. 发明授权

US08762651B2 Maintaining cache coherence in a multi-node, symmetric multiprocessing computer 失效
标题翻译：在多节点对称多处理计算机中维护高速缓存一致性
公开(公告)号：US08762651B2
公开(公告)日：2014-06-24
申请号：US12821578
申请日：2010-06-23
申请人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/084
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译：在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由所述第一计算节点向高速缓存未命中的高速缓存发送对所述高速缓存行的请求; 如果至少两个计算节点具有高速缓存行的正确副本，则选择哪个计算节点将高速缓存行的正确副本发送到第一节点，以及从所选择的计算节点向第一节点发送正确的副本的缓存行; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。

8. 发明授权

US08423736B2 Maintaining cache coherence in a multi-node, symmetric multiprocessing computer 失效
标题翻译：在多节点对称多处理计算机中维护高速缓存一致性
公开(公告)号：US08423736B2
公开(公告)日：2013-04-16
申请号：US12816464
申请日：2010-06-16
申请人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/00
CPC分类号： G06F12/0833
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译：在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由第一计算节点对高速缓存未命中的高速缓存行的请求进行广播; 从每个其他计算节点向所有其他节点传送该节点上的高速缓存行的状态，包括从具有正确副本的任何计算节点向第一节点发送正确的高速缓存行副本; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。

9. 发明申请

US20120210070A1 NON-BLOCKING DATA MOVE DESIGN 审中-公开
标题翻译：非阻塞数据移动设计
公开(公告)号：US20120210070A1
公开(公告)日：2012-08-16
申请号：US13450871
申请日：2012-04-19
申请人： Michael A. Blake , Timothy C. Bronson , Pak-kin Mak , Craig R. Walters
发明人： Michael A. Blake , Timothy C. Bronson , Pak-kin Mak , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/0895
摘要： A mechanism for data buffering is provided. A portion of a cache is allocated as buffer regions, and another portion of the cache is designated as random access memory (RAM). One of the buffer regions is assigned to a processor. A data block is stored to the one of the buffer regions of the cache according an instruction of the processor. The data block is stored from the one of the buffer regions of the cache to the memory.
摘要翻译：提供了一种数据缓冲机制。高速缓存的一部分被分配为缓冲区，高速缓存的另一部分被指定为随机存取存储器（RAM）。一个缓冲区被分配给一个处理器。根据处理器的指令将数据块存储到高速缓冲存储器的一个缓冲区。数据块从缓存的缓冲区中的一个存储到存储器。

10. 发明申请

US20110320738A1 Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer 失效
标题翻译：维持多节点对称多处理计算机中的缓存一致性
公开(公告)号：US20110320738A1
公开(公告)日：2011-12-29
申请号：US12821578
申请日：2010-06-23
申请人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/084
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译：在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由所述第一计算节点向高速缓存未命中的高速缓存发送对所述高速缓存行的请求; 如果至少两个计算节点具有高速缓存行的正确副本，则选择哪个计算节点将高速缓存行的正确副本发送到第一节点，以及从所选择的计算节点向第一节点发送正确的副本的缓存行; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。

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