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1. 发明授权

US07085898B2 Coherency management for a “switchless” distributed shared memory computer system 失效
标题翻译： “无切换”分布式共享内存计算机系统的一致性管理
公开(公告)号：US07085898B2
公开(公告)日：2006-08-01
申请号：US10435776
申请日：2003-05-12
申请人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
发明人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
IPC分类号： G06F12/00 , G06F15/167 , H04L12/43
CPC分类号： G06F12/0813 , G06F12/0831
摘要： An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are launched onto the ring topology simultaneously in both directions. As the messages traverse the nodes on the ring, they trigger remote controllers to perform coherent actions such as cache accesses or directory updates. Messages arriving on each node from both directions are combined with each other and with locally generated responses to form cumulative final responses. Additionally, controllers on the requesting node may perform local coherent actions based on the information conveyed by the returning final responses. Overall system coherency is maintained through the use of a dual token based scheme which provide coherency points to permit multiple non-contending requests for the same data unit. The cache coherency methods described herein further ensure the latest copy of data is always accessed or modified even when multiple copies are present throughout the multi-nodal system structure. Traditional cache management states are extended to include Intervention Master and Multiple Copy status which minimize overall bus utilization. A novel ring protocol is contemplated which efficiently packages coherency information into bus operational responses that also allow simultaneous data transfers in the direction of minimal latency.
摘要翻译：公开了一种用于管理具有多个节点的对称多处理环境中的存储一致性的装置和方法，每个节点包含多个处理器，I / O适配器，主存储器和包括具有顶级缓存的集成开关的系统控制器。节点通过双同心环拓扑互连。任何给定节点上的本地控制器代表该节点上的所述处理器和I / O适配器启动总线操作。 Snoop请求在两个方向同时发送到环形拓扑上。当消息遍历环上的节点时，它们触发远程控制器执行诸如缓存访问或目录更新之类的一致操作。从两个方向到达每个节点的消息彼此组合并且具有本地生成的响应以形成累积的最终响应。此外，请求节点上的控制器可以基于返回的最终响应传达的信息来执行本地一致的动作。通过使用基于双令牌的方案来维护总体系统一致性，其提供相干点以允许对相同数据单元的多个非竞争请求。本文所述的高速缓存一致性方法进一步确保即使在整个多节点系统结构中存在多个副本，始终访问或修改数据的最新副本。传统的缓存管理状态被扩展到包括干预主机和复制状态，从而最大限度地减少总线总线利用率。考虑了一种新颖的环路协议，其有效地将一致性信息包装到总线操作响应中，其也允许以最小延迟的方向同时进行数据传输。

2. 发明授权

US07111130B2 Coherency management for a “switchless” distributed shared memory computer system 失效
公开(公告)号：US07111130B2
公开(公告)日：2006-09-19
申请号：US11402599
申请日：2006-04-12
申请人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
发明人： Michael A. Blake , Pak-kin Mak , Adrian E. Seigler , Gary A. VanHuben
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0831
摘要： A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.

3. 发明授权

US06988173B2 Bus protocol for a switchless distributed shared memory computer system 失效
标题翻译：总线协议用于无交换分布式共享内存计算机系统
公开(公告)号：US06988173B2
公开(公告)日：2006-01-17
申请号：US10435878
申请日：2003-05-12
申请人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
发明人： Michael A. Blake , Steven M. German , Pak-kin Mak , Adrian E. Seigler , Gary A. Van Huben
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system. The bus protocol also allows data to be returned on one of the two rings, with the ring selection determined by the relative placement of the source and destination nodes on each ring, in order to control latency and data bus utilization.
摘要翻译：公开了一种用于由多个节点组成的对称多处理计算机系统的总线协议，每个节点包含多个处理器，I / O设备，主存储器和包括具有顶级高速缓存的集成交换机的系统控制器。节点通过双同心环拓扑互连。总线协议用于以一种允许部分一致性结果与窥探请求和地址并行传送的方式来交换窥探请求和地址，数据，相关性信息和节点之间的操作状态，因为操作沿着每个环转发。每个节点将其自身的一致性结果与在将窥探请求转发之前接收的部分一致性结果相结合，将地址和更新的部分一致性结果合并到环上的下一个节点。该协议允许系统中的每个节点查看最终的一致性结果，而不需要请求节点将这些结果广播到系统中的所有其他节点。总线协议还允许在两个振铃中的一个上返回数据，其中环选择由每个振铃上的源节点和目的节点的相对位置确定，以便控制等待时间和数据总线的利用。

4. 发明授权

US08990507B2 Storing data in a system memory for a subsequent cache flush 有权
公开(公告)号：US08990507B2
公开(公告)日：2015-03-24
申请号：US13495383
申请日：2012-06-13
申请人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
发明人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0895 , G06F12/0804 , G06F12/0817 , G06F12/0891 , G06F12/128
摘要： Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.

5. 发明授权

US08645642B2 Tracking dynamic memory reallocation using a single storage address configuration table 失效
标题翻译：使用单个存储地址配置表跟踪动态内存重新分配
公开(公告)号：US08645642B2
公开(公告)日：2014-02-04
申请号：US12821986
申请日：2010-06-23
申请人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
发明人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
IPC分类号： G06F12/00
CPC分类号： G06F12/0292
摘要： Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.
摘要翻译：使用具有第一寄存器和第二寄存器的单个配置表来跟踪动态存储器去分配包括将第一寄存器设置为活动寄存器，启动从存储器分区的期望存储增量的去分配，在第二寄存器中设置存储增量注册为无效，清除与单个配置表相关联的所有高速缓存，将第二个寄存器设置为活动寄存器，将第一个寄存器设置为非活动寄存器，将第一个寄存器中的所需存储增量设置为无效，将活动寄存器从第二个注册到第一个寄存器，使用单个配置表完成内存取消分配。

6. 发明授权

US08250308B2 Cache coherency protocol with built in avoidance for conflicting responses 失效
标题翻译：缓存一致性协议内置避免冲突的响应
公开(公告)号：US08250308B2
公开(公告)日：2012-08-21
申请号：US12031977
申请日：2008-02-15
申请人： Vesselina K. Papazova , Ekaterina M. Ambroladze , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
发明人： Vesselina K. Papazova , Ekaterina M. Ambroladze , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership state of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.
摘要翻译：该方法包括：当处理器请求遇到本地高速缓存未命中时，向请求节点中的高速缓存发起处理器请求并将处理器请求广播到远程节点，执行每个远程高速缓存的目录搜索以确定目标行的地址的状态，以及指定地址的所有权状态，将目标行的状态返回到请求节点并形成组合响应，并将组合的响应广播到每个远程节点。在获取操作期间，当目录搜索指示远程节点上的IM或目标存储器节点时，数据来自相应的远程高速缓存并且在保护数据的同时被转发到请求节点，并且在存储操作期间，数据是源自请求节点，并且在一致性被建立之后被转发到IM或目标存储器节点时被保护。

7. 发明授权

US07934059B2 Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetching 有权
标题翻译：方法，系统和计算机程序产品，用于防止具有推测性内存提取的多节点系统中的锁定和停顿条件
公开(公告)号：US07934059B2
公开(公告)日：2011-04-26
申请号：US12021781
申请日：2008-01-29
申请人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
发明人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.
摘要翻译：一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到解决冲突的点，而不发出另一个推测性的内存提取请求。随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

8. 发明申请

US20090193198A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PREVENTING LOCKOUT AND STALLING CONDITIONS IN A MULTI-NODE SYSTEM WITH SPECULATIVE MEMORY FETCHING 有权
标题翻译：方法，系统和计算机程序产品，用于在具有分析存储器故障的多节点系统中防止闭锁和停放条件
公开(公告)号：US20090193198A1
公开(公告)日：2009-07-30
申请号：US12021781
申请日：2008-01-29
申请人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
发明人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.
摘要翻译：一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到解决冲突的点，而不发出另一个推测性的内存提取请求。随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

9. 发明申请

US20090083491A1 Storage System and Associated Methods 失效
标题翻译：存储系统及相关方法
公开(公告)号：US20090083491A1
公开(公告)日：2009-03-26
申请号：US11861765
申请日：2007-09-26
申请人： Derrin M. Berger , Michael A. Blake , Garrett M. Drapala , Pak-kin Mak
发明人： Derrin M. Berger , Michael A. Blake , Garrett M. Drapala , Pak-kin Mak
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0851 , G06F12/0855
摘要： A storage system may include storage, a main pipeline to carry data for the storage, and a store pipeline to carry data for the storage. The storage system may also include a controller to prioritize data storage requests for the storage based upon available interleaves and which pipeline is associated with the data storage requests.
摘要翻译：存储系统可以包括存储器，用于存储用于存储数据的主流水线以及用于存储数据的存储流水线。存储系统还可以包括控制器，用于基于可用的交织以及哪个流水线与数据存储请求相关联地对存储的数据存储请求进行优先级排序。

10. 发明授权

US06738872B2 Clustered computer system with deadlock avoidance 有权
标题翻译：具有死锁避免的集群计算机系统
公开(公告)号：US06738872B2
公开(公告)日：2004-05-18
申请号：US09746686
申请日：2000-12-22
申请人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak , Adrian Eric Seigler
发明人： Gary A. Van Huben , Michael A. Blake , Pak-Kin Mak , Adrian Eric Seigler
IPC分类号： G06F1200
CPC分类号： G06F9/524
摘要： A remote resource management system for managing resources in a symmetrical multiprocessing environment having a plurality of clusters of symmetric multiprocessors each of which provides interfaces between cluster nodes of the symmetric multiprocessor system with a local interface and an interface controller. One or more remote storage controllers each has a local interface controller and a local-to-remote data bus. A remote fetch controller is responsible for processing data accesses across the clusters and a remote store controller is responsible for processing data accesses across the clusters. These controllers work in conjunction to provide a deadlock avoidance system for preventing hangs.
摘要翻译：一种用于在具有多个对称多处理器群集的对称多处理环境中管理资源的远程资源管理系统，每个处理器集群在对称多处理器系统的群集节点与本地接口和接口控制器之间提供接口。一个或多个远程存储控制器各自具有本地接口控制器和本地到远程的数据总线。远程提取控制器负责处理跨集群的数据访问，远程存储控制器负责处理跨集群的数据访问。这些控制器协同工作，提供一个防止挂起的死锁避免系统。

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