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1. 发明申请

US20090083491A1 Storage System and Associated Methods 失效
标题翻译：存储系统及相关方法
公开(公告)号：US20090083491A1
公开(公告)日：2009-03-26
申请号：US11861765
申请日：2007-09-26
申请人： Derrin M. Berger , Michael A. Blake , Garrett M. Drapala , Pak-kin Mak
发明人： Derrin M. Berger , Michael A. Blake , Garrett M. Drapala , Pak-kin Mak
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0851 , G06F12/0855
摘要： A storage system may include storage, a main pipeline to carry data for the storage, and a store pipeline to carry data for the storage. The storage system may also include a controller to prioritize data storage requests for the storage based upon available interleaves and which pipeline is associated with the data storage requests.
摘要翻译：存储系统可以包括存储器，用于存储用于存储数据的主流水线以及用于存储数据的存储流水线。存储系统还可以包括控制器，用于基于可用的交织以及哪个流水线与数据存储请求相关联地对存储的数据存储请求进行优先级排序。

2. 发明授权

US07818504B2 Storage system that prioritizes storage requests 失效
标题翻译：存储系统优先处理存储请求
公开(公告)号：US07818504B2
公开(公告)日：2010-10-19
申请号：US11861765
申请日：2007-09-26
申请人： Derrin M. Berger , Michael A. Blake , Garrett M Drapala , Pak-kin Mak
发明人： Derrin M. Berger , Michael A. Blake , Garrett M Drapala , Pak-kin Mak
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0851 , G06F12/0855
摘要： A storage system may include storage, a main pipeline to carry data for the storage, and a store pipeline to carry data for the storage. The storage system may also include a controller to prioritize data storage requests for the storage based upon available interleaves and which pipeline is associated with the data storage requests.
摘要翻译：存储系统可以包括存储器，用于存储用于存储数据的主流水线以及用于存储数据的存储流水线。存储系统还可以包括控制器，用于基于可用的交织以及哪个流水线与数据存储请求相关联地对存储的数据存储请求进行优先级排序。

3. 发明授权

US07254656B2 Method and service and computer program code for broadcast of interface group bring-up in a multiprocessor computer system having multiple nodes 有权
标题翻译：在具有多个节点的多处理器计算机系统中，用于广播接口组的方法和服务以及计算机程序代码
公开(公告)号：US07254656B2
公开(公告)日：2007-08-07
申请号：US10987657
申请日：2004-11-13
申请人： Derrin M. Berger , Jonathan Y. Chen , Thomas E. Gilbert
发明人： Derrin M. Berger , Jonathan Y. Chen , Thomas E. Gilbert
IPC分类号： G06F13/00
CPC分类号： G06F13/4027
摘要： A method and hardware design is disclosed for allowing the bring-up of a large scale system of interfaces that need to undergo a sequence of calibration steps. The method involves the use of a flexible broadcast scheme whereby groups of interfaces within a chip are assigned to groups to which commands can be broadcast. The scheme allows for the maximum amount of flexibility, allowing interfaces to be assigned to multiple groups which can overlap and be subsets of one another, and still allows for groups to be excluded from broadcast commands and be access individually. A method is also disclosed for using a chip-global status summary that can be accessed as any other register on the chip and can report calibration results for an entire chip with only one command. According to the invention a service utilizing the method embodied with code for implementing the method can now be provided.
摘要翻译：公开了用于允许需要经历一系列校准步骤的大规模系统的接口的方法和硬件设计。该方法涉及使用灵活广播方案，由此将芯片内的接口组分配给可以广播命令的组。该方案允许最大的灵活性，允许将接口分配给可以重叠并且彼此子集的多个组，并且仍然允许将组排除在广播命令之外并且被单独访问。还公开了一种用于使用芯片全局状态概要的方法，其可以作为芯片上的任何其他寄存器访问，并且可以仅用一个命令报告整个芯片的校准结果。根据本发明，现在可以提供利用具有用于实现该方法的代码体现的方法的服务。

4. 发明申请

US20090083490A1 System to Improve Data Store Throughput for a Shared-Cache of a Multiprocessor Structure and Associated Methods 审中-公开
标题翻译：用于提高多处理器结构和相关方法的共享缓存的数据存储吞吐量的系统
公开(公告)号：US20090083490A1
公开(公告)日：2009-03-26
申请号：US11861814
申请日：2007-09-26
申请人： Derrin M. Berger , Michael F. Fee , Park-kin Mak
发明人： Derrin M. Berger , Michael F. Fee , Park-kin Mak
IPC分类号： G06F12/08
CPC分类号： G06F12/0882 , G06F12/084 , G06F12/0855
摘要： A system to improve data store throughput for a shared-cache of a multiprocessor structure that may include a controller to find and compare a last data store address for a last data store with a next data store address for a next data store. The system may also include a main pipeline to receive the last data store, and to receive the next data store if the next data store address differs substantially from the last data store address. The system may further include a store pipeline to receive the next data store if the next data store address is substantially similar to the last data store address.
摘要翻译：一种用于提高多处理器结构的共享高速缓存的数据存储吞吐量的系统，其可以包括控制器，以找到并比较最后数据存储的最后数据存储地址与下一个数据存储的下一数据存储地址。系统还可以包括用于接收最后数据存储的主流水线，并且如果下一个数据存储地址与最后数据存储地址显着不同，则接收下一个数据存储。如果下一个数据存储地址基本上类似于最后的数据存储地址，系统还可以包括存储流水线以接收下一个数据存储。

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