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11. 发明授权

US06762063B2 Method of fabricating non-volatile ferroelectric transistors 有权
标题翻译：制造非易失性铁电晶体管的方法
公开(公告)号：US06762063B2
公开(公告)日：2004-07-13
申请号：US10395368
申请日：2003-03-24
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L2100
CPC分类号： H01L29/6684 , H01L21/28291 , H01L29/78391
摘要： A method of fabricating a non-volatile ferroelectric memory transistor includes forming a bottom electrode; depositing a ferroelectric layer over an active region beyond the margins of the bottom electrode; depositing a top electrode on the ferroelectric layer; and metallizing the structure to form a source electrode, a gate electrode and a drain electrode. A non-volatile ferroelectric memory transistor includes a bottom electrode formed above a gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; and a top electrode formed on said ferroelectric layer.
摘要翻译：制造非挥发性铁电存储晶体管的方法包括：形成底电极; 在超过底部电极的边缘的有源区域上沉积铁电层; 在铁电层上沉积顶部电极; 并且将该结构金属化以形成源电极，栅电极和漏电极。非挥发性铁电存储晶体管包括形成在栅极区域上方的底部电极，其中底部电极在外围边界内具有预定区域; 延伸超过底部电极周边边界的铁电层; 以及形成在所述铁电层上的顶部电极。

12. 发明授权

US06711049B1 One transistor cell FeRAM memory array 失效
标题翻译：一个晶体管单元FeRAM存储器阵列
公开(公告)号：US06711049B1
公开(公告)日：2004-03-23
申请号：US10282985
申请日：2002-10-28
申请人： Sheng Teng Hsu , Jong-Jan Lee , Fengyan Zhang , Nobuyoshi Awaya
发明人： Sheng Teng Hsu , Jong-Jan Lee , Fengyan Zhang , Nobuyoshi Awaya
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A one-transistor FeRAM memory cell array includes an array of ferroelectric transistors arranged in rows and columns, each transistor having a source, a drain, a channel, a gate oxide layer over the channel and a ferroelectric stack formed on the gate oxide layer; word lines connecting the gate ferroelectric stack top electrodes of transistors in a row of the array; a connection to the channel of all transistors in the array formed by a substrate well; a set of first bit lines connecting the sources of all transistors in a column of the array; and a set of second bit lines connecting the drains of all transistors in a column of the array; wherein the ferroelectric stack has opposed edges, which, when projected to a level of the source, drain and channel, are coincident with an abutted edge of the source and the channel and the drain and the channel, respectively.
摘要翻译：单晶体管FeRAM存储单元阵列包括以行和列布置的铁电晶体管阵列，每个晶体管具有源极，漏极，沟道，沟道上的栅极氧化物层和形成在栅极氧化物层上的铁电堆叠; 连接阵列中的晶体管的栅极铁电叠层顶部电极的字线; 连接到由衬底阱形成的阵列中的所有晶体管的沟道; 连接阵列的列中的所有晶体管的源的一组第一位线; 以及连接阵列中的所有晶体管的漏极的一组第二位线; 其中所述铁电堆叠具有相对的边缘，当所述铁电堆叠被投影到所述源极的水平面时，所述漏极和沟道分别与所述源极和所述沟道以及所述漏极和所述沟道的邻接边缘重合。

13. 发明授权

US06673664B2 Method of making a self-aligned ferroelectric memory transistor 失效
标题翻译：制造自对准铁电存储晶体管的方法
公开(公告)号：US06673664B2
公开(公告)日：2004-01-06
申请号：US09978487
申请日：2001-10-16
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
IPC分类号： H01L218238
CPC分类号： H01L29/51 , H01L21/28291 , H01L21/31691 , H01L27/11502 , H01L27/11507 , H01L29/516
摘要： A method of making a self-aligned ferroelectric memory transistor includes preparing a substrate, shallow trench isolation, n the polysilicon; and forming a gate stack, including: depositing a layer of silicon nitride; selectively etching the silicon nitride, the bottom electrode and the polysilicon; selectively etching the polysilicon to the level of the first dielectric layer; and implanting and activating ions to form a source region and a drain region; forming a sidewall barrier layer; depositing a layer of ferroelectric material; forming a top electrode structure on the ferroelectric material; and finishing the structure, including passivation, oxide depositing and metallization.
摘要翻译：制造自对准铁电存储晶体管的方法包括制备衬底，浅沟槽隔离，n多晶硅; 以及形成栅叠层，包括：沉积氮化硅层; 选择性地蚀刻氮化硅，底部电极和多晶硅; 选择性地将多晶硅蚀刻到第一介电层的水平面; 以及植入和激活离子以形成源区和漏区; 形成侧壁阻挡层; 沉积一层铁电材料; 在铁电材料上形成顶部电极结构; 并完成结构，包括钝化，氧化物沉积和金属化。

14. 发明授权

US06616857B2 C-axis oriented lead germanate film 失效
标题翻译： C轴取向锗酸铅膜
公开(公告)号：US06616857B2
公开(公告)日：2003-09-09
申请号：US09942203
申请日：2001-08-29
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01B108
CPC分类号： H01L21/31691 , C23C16/40 , H01L21/31604 , Y10S438/933 , Y10T428/12674 , Y10T428/12701 , Y10T428/12875
摘要： A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7 A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.
摘要翻译：铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均粒径为约0.5微米，晶粒尺寸均匀度的偏差小于10％。对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。这些胶片还显示出无疲劳特性：在1x109个开关周期内没有观察到疲劳。泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。

15. 发明授权

US06602720B2 Single transistor ferroelectric transistor structure with high-K insulator and method of fabricating same 失效
标题翻译：具有高K绝缘体的单晶体管铁电晶体管结构及其制造方法
公开(公告)号：US06602720B2
公开(公告)日：2003-08-05
申请号：US09820023
申请日：2001-03-28
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L2100
CPC分类号： H01L29/4983 , H01L21/02189 , H01L21/02197 , H01L21/02271 , H01L21/0228 , H01L21/28291 , H01L21/31053 , H01L21/31604 , H01L21/31691 , H01L29/516 , H01L29/66545 , H01L29/78391
摘要： A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.
摘要翻译：提供了具有铁电栅极和高k绝缘体的铁电晶体管栅极结构。高k绝缘体可以用作栅极电介质和绝缘体，以减少或消除氧或氢扩散到铁电栅极中。还提供了形成铁电栅极结构的方法。该方法包括以下步骤：形成牺牲栅极结构，去除牺牲栅极结构，沉积高k绝缘体，沉积铁电材料，使用CMP抛光铁电材料，以及形成覆盖铁电材料的顶部电极。

16. 发明授权

US06555456B2 Method of forming iridium conductive electrode/barrier structure 失效
公开(公告)号：US06555456B2
公开(公告)日：2003-04-29
申请号：US10037192
申请日：2001-11-09
申请人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
发明人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
IPC分类号： H01L213205
CPC分类号： H01L29/456 , H01L21/28291 , H01L28/55 , H01L28/65
摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

17. 发明授权

US06441417B1 Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same 失效
标题翻译：用于非易失性存储器应用的ZrO 2上的单个c轴PGO薄膜及其制造方法
公开(公告)号：US06441417B1
公开(公告)日：2002-08-27
申请号：US09820022
申请日：2001-03-28
申请人： Fengyan Zhang , Yanjun Ma , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
发明人： Fengyan Zhang , Yanjun Ma , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
IPC分类号： H01L2972
CPC分类号： H01L21/28291 , H01L21/31604 , H01L21/31691 , H01L28/56 , H01L29/516
摘要： A thin film structure includes a substantially single-phase, c-axis PGO film on an insulator for use in metal ferroelectric insulator semiconductor single transistor non-volatile memory applications. The PGO on insulator structure can also be used in capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. In a preferred embodiment, the PGO film is deposited on a Zirconium Oxide insulator layer.
摘要翻译：薄膜结构包括用于金属铁电绝缘体半导体单晶体管非易失性存储器应用的绝缘体上的基本单相c轴PGO膜。 PGO绝缘体结构也可用于电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件中。在优选实施例中，PGO膜沉积在氧化锆绝缘体层上。

18. 发明授权

US06410343B1 C-axis oriented lead germanate film and deposition method 失效
标题翻译： C轴取向锗酸铅膜和沉积法
公开(公告)号：US06410343B1
公开(公告)日：2002-06-25
申请号：US09301420
申请日：1999-04-28
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L21/31691 , C23C16/40 , H01L21/31604 , Y10S438/933 , Y10T428/12674 , Y10T428/12701 , Y10T428/12875
摘要： A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.
摘要翻译：铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均粒径为约0.5微米，晶粒尺寸均匀度的偏差小于10％。对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。这些胶片还显示出无疲劳特性：在1x109个开关周期内没有观察到疲劳。泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。

19. 发明授权

US07905013B2 Method for forming an iridium oxide (IrOx) nanowire neural sensor array 有权
标题翻译：形成氧化铱（IrOx）纳米线神经传感器阵列的方法
公开(公告)号：US07905013B2
公开(公告)日：2011-03-15
申请号：US11809959
申请日：2007-06-04
申请人： Fengyan Zhang , Bruce D. Ulrich , Wei Gao , Sheng Teng Hsu
发明人： Fengyan Zhang , Bruce D. Ulrich , Wei Gao , Sheng Teng Hsu
IPC分类号： H01K3/10
CPC分类号： A61N1/0543 , B82Y15/00 , B82Y30/00 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T428/24998
摘要： An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.
摘要翻译：提供氧化铱（IrOx）纳米线神经传感器阵列及相关制造方法。该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。基板可以是诸如Si，SiO 2，石英，玻璃或聚酰亚胺的材料，并且导电层是诸如ITO，SnO 2，ZnO，TiO 2，掺杂的ITO，掺杂的SnO 2，掺杂的ZnO，掺杂的TiO 2，TiN， TaN，Au，Pt或Ir。电介质层被选择性地湿蚀刻，与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面，并且可以被成形为圆形，矩形或椭圆形。

20. 发明申请

US20090024182A1 IrOx Nanostructure Electrode Neural Interface Optical Device 有权
标题翻译： IrOx纳米结构电极神经界面光学器件
公开(公告)号：US20090024182A1
公开(公告)日：2009-01-22
申请号：US12240501
申请日：2008-09-29
申请人： Fengyan Zhang , Sheng Teng Hsu
发明人： Fengyan Zhang , Sheng Teng Hsu
IPC分类号： A61N1/36
CPC分类号： C30B25/00 , A61N1/0543 , B82Y5/00 , B82Y10/00 , B82Y30/00 , C30B29/16 , C30B29/605 , Y10S977/811 , Y10S977/904 , Y10S977/932
摘要： An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x≦4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.
摘要翻译：提供了具有氧化铱（IrOx）电极神经接口的光学器件及相应的制造方法。该方法提供了一个衬底并且形成了覆盖衬底的第一导电电极。具有第一电接口的光电器件连接到第一电极。光电器件的第二电接口连接到形成在光伏器件上的第二导电电极。形成了覆盖第二电极的神经界面单晶IrOx纳米结构阵列，其中x <= 4。 IrOx纳米结构可以部分地涂覆有电绝缘体，例如SiO 2，SiN，TiO 2或旋转玻璃（SOG），留下IrOx远端暴露。在一个方面，为了定向IrOx纳米结构的生长方向，形成了由诸如LiNbO 3，LiTaO 3或SA的材料制成的第二电极表面上的缓冲层。

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