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11. 发明申请

US20120299188A1 WIRING STRUCTURE AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：导线结构及形成结构的方法
公开(公告)号：US20120299188A1
公开(公告)日：2012-11-29
申请号：US13114079
申请日：2011-05-24
申请人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L21/76816 , H01L21/76843 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.
摘要翻译：公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。较厚的上部位于布线结构和相邻电介质材料之间的接合处。较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。

12. 发明申请

US20120218030A1 METHOD FOR MANAGING CIRCUIT RELIABILITY 失效
标题翻译：管理电路可靠性的方法
公开(公告)号：US20120218030A1
公开(公告)日：2012-08-30
申请号：US13034758
申请日：2011-02-25
申请人： Fen Chen , Kai D. Feng , Zhong-Xiang He
发明人： Fen Chen , Kai D. Feng , Zhong-Xiang He
IPC分类号： H03K19/003
CPC分类号： H03K19/00307
摘要： Managing reliability of a circuit that includes a plurality of duplicate components, with less than all of the components being active at any time during circuit operation, where reliability is managed by operating, by the circuit, with a first set of components that includes a predefined number of components; selecting, without altering circuit performance and in accordance with a circuit reliability protocol, a second set of components with which to operate, including activating an inactive component and deactivating an active component of the first set of components; and operating, by the circuit, with the second set of components.
摘要翻译：管理包括多个重复部件的电路的可靠性，其中小于所有组件在电路操作期间的任何时间处于活动状态，其中可靠性由电路通过第一组组件来管理，该组件包括预定义的组件数量; 根据电路可靠性协议选择不改变电路性能的第二组组件，包括激活非活动组件和去激活第一组组件的活动组件; 并通过电路与第二组元件一起操作。

13. 发明授权

US08018017B2 Thermo-mechanical cleavable structure 有权
标题翻译：热机械可切割结构
公开(公告)号：US08018017B2
公开(公告)日：2011-09-13
申请号：US10905905
申请日：2005-01-26
申请人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
发明人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
IPC分类号： H01L31/058
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.
摘要翻译：提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。热机械应力还由于由其产生的气体引起的相变而收缩。当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

14. 发明授权

US07998828B2 Method of forming metal ion transistor 失效
标题翻译：形成金属离子晶体管的方法
公开(公告)号：US07998828B2
公开(公告)日：2011-08-16
申请号：US12725817
申请日：2010-03-17
申请人： Fen Chen , Armin Fischer
发明人： Fen Chen , Armin Fischer
IPC分类号： H01L21/34 , H01L29/12 , H01L27/148 , H01L51/40 , H01L21/335 , H01L21/8232 , H01L21/339 , H01L21/00 , H01L21/84 , H01L21/76 , H01L21/20 , H01L21/36
CPC分类号： H01L45/00
摘要： A method of forming a metal ion transistor comprises forming a first electrode in a first isolation layer; forming a second isolation layer over the first isolation layer; forming a first cell region of a low dielectric constant (low-k) dielectric over the first electrode in the second isolation layer, the first cell region isolated from the second isolation layer; forming a cap layer over the second isolation layer and the first cell region, at least thinning the cap layer over the first cell region; depositing a layer of the low-k dielectric over the second isolation layer and the first cell region; forming metal ions in the low-k dielectric layer; patterning the low-k dielectric layer to form a second cell region; sealing the second cell region using a liner; and forming a second electrode contacting the second cell region and a third electrode contacting the second cell region.
摘要翻译：一种形成金属离子晶体管的方法包括在第一隔离层中形成第一电极; 在所述第一隔离层上形成第二隔离层; 在所述第二隔离层中的所述第一电极上形成低介电常数（低k）电介质的第一电池区，所述第一电池区与所述第二隔离层隔离; 在所述第二隔离层和所述第一单元区域上形成盖层，至少使所述盖层在所述第一单元区域上变薄; 在所述第二隔离层和所述第一单元区域上沉积所述低k电介质层; 在低k电介质层中形成金属离子; 图案化低k电介质层以形成第二电池区; 使用衬垫密封第二电池区域; 以及形成与第二单元区域接触的第二电极和与第二单元区域接触的第三电极。

15. 发明授权

US07795679B2 Device structures with a self-aligned damage layer and methods for forming such device structures 失效
标题翻译：具有自对准损伤层的装置结构和用于形成这种装置结构的方法
公开(公告)号：US07795679B2
公开(公告)日：2010-09-14
申请号：US12178766
申请日：2008-07-24
申请人： Ethan H. Cannon , Fen Chen
发明人： Ethan H. Cannon , Fen Chen
IPC分类号： H01L31/0392 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/26506 , H01L29/6659 , H01L29/66659 , H01L29/7842 , H01L29/7848
摘要： Device structures with a self-aligned damage layer and methods of forming such device structures. The device structure first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate. A third doped region of opposite conductivity type laterally separates the first doped region from the second doped region. A gate structure is disposed on a top surface of the substrate and has a vertically stacked relationship with the third doped region. A first crystalline damage layer is defined within the semiconductor material of the substrate. The first crystalline damage layer has a first plurality of voids surrounded by the semiconductor material of the substrate. The first doped region is disposed vertically between the first crystalline damage layer and the top surface of the substrate. The first crystalline damage layer does not extend laterally into the third doped region.
摘要翻译：具有自对准损伤层的装置结构和形成这种装置结构的方法。该器件结构是限定在衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。相反导电类型的第三掺杂区域将第一掺杂区域与第二掺杂区域横向分离。栅极结构设置在衬底的顶表面上，并且与第三掺杂区域具有垂直堆叠的关系。第一晶体损伤层被限定在衬底的半导体材料内。第一晶体损伤层具有由衬底的半导体材料包围的第一多个空隙。第一掺杂区域垂直地设置在第一晶体损伤层和衬底的顶表面之间。第一晶体损伤层不横向延伸到第三掺杂区域。

16. 发明授权

US07677749B2 Optical plate and backlight module using the same 失效
标题翻译：光板和背光模组使用相同
公开(公告)号：US07677749B2
公开(公告)日：2010-03-16
申请号：US11845790
申请日：2007-08-28
申请人： Shao-Han Chang , Fen Chen
发明人： Shao-Han Chang , Fen Chen
IPC分类号： F21V8/00 , G09F13/04
CPC分类号： G02B19/0066 , G02B5/0278 , G02B6/0021 , G02B6/003 , G02B19/0028 , G02B19/0071 , G02F1/133603 , G02F1/133606
摘要： An exemplary optical plate includes at least one transparent plate unit. The transparent plate unit includes a light output surface, a bottom surface, a plurality of through holes and at least one lamp-receiving portion. The light output surface is opposite to the bottom surface. Each of the through holes communicates the light output surface with the bottom surface. The lamp-receiving portion is defined in the bottom surface. A backlight module using the present optical plate is also provided.
摘要翻译：示例性的光学板包括至少一个透明板单元。透明板单元包括光输出表面，底表面，多个通孔和至少一个灯接收部分。光输出表面与底表面相对。每个通孔将光输出表面与底表面连通。灯接收部分限定在底面。还提供了使用本发明的光学板的背光模块。

17. 发明申请

US20080285277A1 Bottom lighting type backlight module having illumination and heat dissipation spaces and plurality of through-holes therein 审中-公开
标题翻译：具有照明和散热空间的底部照明型背光模块和其中的多个通孔
公开(公告)号：US20080285277A1
公开(公告)日：2008-11-20
申请号：US12220380
申请日：2008-07-24
申请人： Shao-Han Chang , Fen Chen
发明人： Shao-Han Chang , Fen Chen
IPC分类号： F21V7/04
CPC分类号： G02F1/133608 , G02F2001/133628
摘要： An exemplary bottom lighting type backlight module includes a frame, a plurality of light sources, a reflecting sheet and at least one optical sheet. The frame includes a base and a plurality of sidewalls extending from the peripheral of the base to define an opening. The base defines a plurality of guide holes. Each optical sheet is disposed on the opening of the frame. The at least one optical sheet and the frame collectively define a chamber. The reflecting sheet is supported by the sidewalls, for partitioning the chamber into an illumination space and a heat dissipation space. The reflecting sheet defines a plurality of through holes therein. The light sources are arranged on the base of the frame under the reflecting sheet according to the through holes, illuminating light through the through holes towards the at least one optical sheet.
摘要翻译：示例性的底部照明型背光模块包括框架，多个光源，反射片和至少一个光学片。框架包括从基部的周边延伸以限定开口的基部和多个侧壁。基部限定多个引导孔。每个光学片设置在框架的开口上。所述至少一个光学片和所述框共同地限定一个室。反射片由侧壁支撑，用于将室分隔成照明空间和散热空间。反射片在其中限定多个通孔。光源根据通孔布置在反射片下方的框架底部，通过通孔朝向至少一个光学片照射光。

18. 发明申请

US20080173975A1 PROGRAMMABLE RESISTOR, SWITCH OR VERTICAL MEMORY CELL 审中-公开
标题翻译：可编程电阻器，开关或垂直存储器单元
公开(公告)号：US20080173975A1
公开(公告)日：2008-07-24
申请号：US11625607
申请日：2007-01-22
申请人： Fen Chen , Armin Fischer , Jason P. Gill
发明人： Fen Chen , Armin Fischer , Jason P. Gill
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L45/1266 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/145 , H01L45/1616 , H01L45/1683
摘要： Disclosed are embodiments of a device and method of forming the device that utilize metal ion migration under controllable conditions. The device embodiments comprise two metal electrodes separated by one or more different dielectric materials. One electrode is sealed from the dielectric material, the other is not. The device is adapted to allow controlled migration of embedded metal ions from the unsealed electrode into dielectric material to form a conductive path under field between the electrodes and, thereby, to decrease the resistance of the dielectric material. Reversing the field causes the metal ions to reverse their migration, to break the conductive metallic path between the electrodes and, thereby, to increase the resistance of the dielectric material. Thus, the device can comprise a simple switch or programmable resistor. Additionally, by monitoring the resistance change, a two-state, two-terminal, silicon technology-compatible, flash memory device with a very simple tuning process can be created.
摘要翻译：披露了在可控条件下形成利用金属离子迁移的装置的装置和方法的实施例。器件实施例包括由一种或多种不同电介质材料隔开的两个金属电极。一个电极与介电材料密封，另一个不是。该器件适于允许将嵌入的金属离子从非密封电极受控地迁移到电介质材料中，以形成电极之间的导电路径，从而降低电介质材料的电阻。反转场导致金属离子反向迁移，以破坏电极之间的导电金属路径，从而增加电介质材料的电阻。因此，该装置可以包括简单的开关或可编程电阻器。另外，通过监控电阻变化，可以创建具有非常简单的调整过程的两状态，两端，硅技术兼容的闪存器件。

19. 发明申请

US20080001620A1 METHOD AND APPARATUS FOR IMPEDANCE MATCHING IN TRANSMISSION CIRCUITS USING TANTALUM NITRIDE RESISTOR DEVICES 有权
标题翻译：使用氮化钛电阻器件在传输电路中阻抗匹配的方法和装置
公开(公告)号：US20080001620A1
公开(公告)日：2008-01-03
申请号：US11427798
申请日：2006-06-30
申请人： Fen Chen , Kai D. Feng , Robert J. Gauthier , Tom C. Lee
发明人： Fen Chen , Kai D. Feng , Robert J. Gauthier , Tom C. Lee
IPC分类号： H03K19/003
CPC分类号： H03K19/018571
摘要： A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.
摘要翻译：一种用于微调高速电路中的阻抗匹配装置的方法包括：确定与在被测电路中用作阻抗匹配装置的第一氮化钽（TaN）电阻相关联的电参数，并将确定的与第一TaN相关的电参数进行比较电阻到所需的电参数设计值。通过施加微调电压来改变第一TaN电阻器的电阻值，其中微调电压基于第一TaN电阻器的耐电压特性曲线。然后确定第一TaN电阻器的改变的电阻值是否使电参数等于其期望的设计值，并且重复通过施加微调电压来改变第一TaN电阻器的电阻值，直到电参数等于其期望的设计值。

20. 发明授权

US07231617B2 Determination of grain sizes of electrically conductive lines in semiconductor integrated circuits 有权
标题翻译：确定半导体集成电路中导电线的晶粒尺寸
公开(公告)号：US07231617B2
公开(公告)日：2007-06-12
申请号：US10711418
申请日：2004-09-17
申请人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
IPC分类号： G06F17/50
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines can be formed on a wafer each of which comprises multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections of all the lines. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments can be determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.
摘要翻译：用于评估半导体集成电路中的线路的新型结构和方法。可以在每个包括多个线段的晶片上形成第一组多条线。所有线段长度相同。测量线路段的电阻。然后，基于所有线的所有部分的电阻来确定第一线几何形状调整。第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。相同长度和厚度的第二组多条线可以形成在同一晶片上。然后，可以基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

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