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11. 发明申请

US20070046338A1 Buffer circuit with multiple voltage range 失效
标题翻译：具有多电压范围的缓冲电路
公开(公告)号：US20070046338A1
公开(公告)日：2007-03-01
申请号：US11215663
申请日：2005-08-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
IPC分类号： H03B1/00
CPC分类号： H03K19/018585 , H03K19/018521 , H03K19/018592
摘要： A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of the first buffer connects to an external pad of the buffer circuit, and an output of the second buffer connects to the pad via the isolation circuit. The buffer circuit is selectively operative in at least a first mode or a second mode in response to at least a first control signal. The isolation circuit is operative in the first mode to substantially isolate the second buffer from the external pad and is operative in the second mode to connect the output of the second buffer to the external pad.
摘要翻译：在多个电源电压电平下工作的缓冲电路包括第一和第二缓冲器，第一缓冲器被配置为与第一电压源一起操作，第二缓冲器与第二电压源一起工作。缓冲电路还包括可控隔离电路。第一缓冲器的输出连接到缓冲电路的外部焊盘，第二缓冲器的输出经由隔离电路连接到焊盘。响应于至少第一控制信号，缓冲器电路以至少第一模式或第二模式选择性地工作。隔离电路在第一模式下工作，以将第二缓冲器与外部焊盘基本隔离，并且在第二模式下工作，以将第二缓冲器的输出连接到外部焊盘。

12. 发明申请

US20060170462A1 RELIABILITY COMPARATOR WITH HYSTERESIS 有权
标题翻译：可靠性比较器与HYSTERESIS
公开(公告)号：US20060170462A1
公开(公告)日：2006-08-03
申请号：US11047388
申请日：2005-01-31
申请人： Dipankar Bhattacharya , John Kriz , Bernard Morris , William Wilson
发明人： Dipankar Bhattacharya , John Kriz , Bernard Morris , William Wilson
IPC分类号： H03K5/22
CPC分类号： H03K3/02337 , H03K3/3565
摘要： A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal. A hysteresis circuit is included in the comparator circuit for selectively controlling a switching threshold of the comparator, relative to the input signal, as a function of the output signal of the comparator. The comparator circuit includes a voltage clamp operative to limit a voltage applied to one or more devices in the control circuit, the comparator, and/or the hysteresis circuit to less than the second voltage.
摘要翻译：比较器电路包括连接到提供第一电压的第一源的参考发生器。参考发生器用于产生参考信号并且包括响应于第一控制信号选择性地以至少第一模式或第二模式操作的控制电路，其中在第一模式中不产生参考信号，并且在第二模式，参考发生器用于产生参考信号。比较器电路还包括连接到提供第二电压的第二源的比较器，第二电压小于第一电压。比较器用于接收参考信号和输入信号，并且产生作为输入信号和参考信号之间的比较的函数的输出信号。比较器电路中包括滞后电路，用于根据比较器的输出信号选择性地控制比较器相对于输入信号的切换阈值。比较器电路包括电压钳位器，用于将施加到控制电路，比较器和/或滞后电路中的一个或多个器件的电压限制为小于第二电压。

13. 发明申请

US20060145749A1 Bias circuit having reduced power-up delay 审中-公开
标题翻译：偏置电路具有降低的上电延迟
公开(公告)号：US20060145749A1
公开(公告)日：2006-07-06
申请号：US11026426
申请日：2004-12-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
IPC分类号： G05F1/10
CPC分类号： G05F3/205
摘要： A bias circuit includes a reference generator for generating a bias signal at an output of the reference generator. The reference generator is selectively operable a first mode or a second mode in response to a first control signal applied to the reference generator, wherein in the first mode of operation, the reference generator is disabled, and in the second mode of operation, the reference generator is operative to generate the bias signal. The bias circuit further includes a shunt circuit connected to the reference generator. The shunt circuit is configured to provide a source of current to assist in charging the output of the reference generator to a quiescent operating level during the second mode of operation. The shunt circuit, in response to a second control signal applied thereto, is operable for a selected period time after the reference generator transitions from the first mode of operation to the second mode of operation.
摘要翻译：偏置电路包括用于在参考发生器的输出处产生偏置信号的参考发生器。参考发生器响应于施加到参考发生器的第一控制信号而选择性地操作第一模式或第二模式，其中在第一操作模式中，参考发生器被禁用，并且在第二操作模式中，发生器用于产生偏置信号。偏置电路还包括连接到参考发生器的分流电路。分流电路被配置为提供电流源以帮助在第二操作模式期间将参考发生器的输出充电到静止工作电平。分流电路响应于施加到其上的第二控制信号可在参考发生器从第一操作模式转换到第二操作模式之后的所选时段内操作。

14. 发明申请

US20060103427A1 Overvoltage tolerant input buffer 有权
公开(公告)号：US20060103427A1
公开(公告)日：2006-05-18
申请号：US10988103
申请日：2004-11-12
申请人： Dipankar Bhattacharya , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , John Kriz , Bernard Morris
IPC分类号： H03K19/094
CPC分类号： H03K19/00315
摘要： When a P-channel pass gate transistor is added in parallel to an N-channel pass gate, the resulting circuit improves overvoltage tolerance of an input buffer. A simple bias circuit including two small transistors controls a gate of this P-channel pass gate transistor in such a way that it is turned OFF when an overvoltage is applied, but turned ON when a normal voltage is applied. Another embodiment has two N-channel devices (M12, M13) coupled in series with each other and one of the N-channel devices (M13) being configured in a “turned off” position, by coupling the source and gate terminals to a ground voltage (VSS) and providing the supply voltage (VDD) at the gate terminal of another N-channel device (M12), whereby the device M12 protects the device M13 from overvoltage.

15. 发明申请

US20050134364A1 Reference compensation circuit 有权
标题翻译：参考补偿电路
公开(公告)号：US20050134364A1
公开(公告)日：2005-06-23
申请号：US10744801
申请日：2003-12-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Jeffrey Nagy , Stefan Siegel
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Jeffrey Nagy , Stefan Siegel
IPC分类号： G05F3/02 , G05F3/24
CPC分类号： G05F3/245 , G05F3/247
摘要： A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit. The control circuit is operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively.
摘要翻译：补偿电路包括参考电路，该参考电路包括参考NMOS器件和参考PMOS器件。参考电路可操作以产生第一参考信号和第二参考信号，第一参考信号是参考NMOS器件的处理特性，电压特性和温度特性中的至少一个的函数，第二参考信号信号是参考PMOS器件的工艺特性，电压特性和温度特性中的至少一个的函数。补偿电路还包括连接到参考电路的控制电路。控制电路可操作以接收第一和第二参考信号并产生一个或多个输出信号，用于补偿至少一个NMOS器件的工艺特性，电压特性和温度特性中的至少一个的变化，并且在响应于第一和第二参考信号，要补偿的电路中的至少一个PMOS器件可连接到控制电路。

16. 发明申请

US20060012406A1 Output buffer with selectable slew rate 有权
标题翻译：输出缓冲器，可选择转换速率
公开(公告)号：US20060012406A1
公开(公告)日：2006-01-19
申请号：US10891048
申请日：2004-07-15
申请人： Carol Huber , John Kriz , Brian Lacey , Bernard Morris
发明人： Carol Huber , John Kriz , Brian Lacey , Bernard Morris
IPC分类号： H03B1/00
CPC分类号： H03K17/163
摘要： A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.
摘要翻译：用于具有可调节转换速率控制的集成电路的缓冲器设计，但与具有压摆率控制的常规缓冲器相比，制造空间要小得多。将新的压摆率控制电路设计添加到互补金属氧化物半导体CMOS缓冲器中以在缓冲器中实现转换速率控制（例如，在高转换速率和低压摆率之间进行选择）。新的压摆率控制电路需要明显较少的制造空间，并且当应用于给定集成电路中的每个缓冲器（例如可沿着集成电路的周边放置的输入/输出缓冲器）时，节省的成本是非同寻常的。

17. 发明授权

US07902904B2 Bias circuit scheme for improved reliability in high voltage supply with low voltage device 有权
标题翻译：偏压电路方案，用于提高低压电源的可靠性
公开(公告)号：US07902904B2
公开(公告)日：2011-03-08
申请号：US12330828
申请日：2008-12-09
申请人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
发明人： Pankaj Kumar , Makeshwar Kothandaraman , Dipankar Bhattacharya , John Kriz , Jeffrey J. Nagy , Pramod Elamannu Parameswaran
IPC分类号： G05F1/10
CPC分类号： G05F3/16
摘要： Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.
摘要翻译：公开了一种偏置电路，其中第一电阻器连接在电源电压和反馈节点之间。电阻器连接在反馈节点和参考电源电压之间。电阻之间的连接限定了至少一个偏置电压。第二电阻器连接在反馈节点和第一漏极节点之间。第一场效应晶体管具有第一栅极节点，第一漏极节点和第一源节点。门节点连接到第一电源电压。第二场效应晶体管具有第二栅极节点，第二漏极节点和第二源节点。第二排水节点连接到第一源节点。第二栅极节点连接到偏置电压。第二源节点连接到输出信号节点。输出信号节点能够经历过冲电压。

18. 发明申请

US20060203405A1 Power pin to power pin electro-static discharge (ESD) clamp 有权
公开(公告)号：US20060203405A1
公开(公告)日：2006-09-14
申请号：US11076850
申请日：2005-03-11
申请人： Dipankar Bhattacharya , John Kriz , Che Leung , Duane Loeper , Yehuda Smooha
发明人： Dipankar Bhattacharya , John Kriz , Che Leung , Duane Loeper , Yehuda Smooha
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An ESD clamp circuit for use between separate power rails. An ESD clamp is based on a wide nMOSFET. A symmetrical circuit is designed vis-à-vis the two power rails, with respect to ground, allowing discharge of an ESD surge in both polarities of stress. An nMOSFET device drives the gate of a large nMOSFET (e.g., having a device width between 1000 and 10,000 microns). The large power rail-to-power rail nMOSFET has its gate controlled by the output inverter stage of either ESD detection circuit connected to a respective power supply rail. The gate is switched to a common ground during normal operation of the integrated circuit.

19. 发明申请

US20100271118A1 I/O Buffer with Low Voltage Semiconductor Devices 失效
标题翻译：带低压半导体器件的I / O缓冲器
公开(公告)号：US20100271118A1
公开(公告)日：2010-10-28
申请号：US12428556
申请日：2009-04-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
IPC分类号： G05F1/10
CPC分类号： H03K17/0822 , H03K19/018528
摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.
摘要翻译：所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。从缓冲器的工作电压产生第一和第二偏置电压。从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压缓冲。第三和第四偏置电压分别提供给第一和第二过压保护电路。

20. 发明申请

US20060044028A1 Programmable reset signal that is independent of supply voltage ramp rate 有权
标题翻译：独立于电源电压斜坡率的可编程复位信号
公开(公告)号：US20060044028A1
公开(公告)日：2006-03-02
申请号：US10925613
申请日：2004-08-25
申请人： Dipankar Bhattacharya , John Kriz , Duane Loeper , Antonio Marques
发明人： Dipankar Bhattacharya , John Kriz , Duane Loeper , Antonio Marques
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage. The voltage level detector is configured such that the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage. The second voltage is less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.
摘要翻译：用于产生复位信号的PUR电路包括用于接收参考电压的第一节点和用于接收相对于参考电压参考的电源电压的第二节点。电路还包括耦合在第一节点和第三节点之间的电压电平检测器，电压电平检测器被配置为在第三节点处产生第一控制信号。电压电平检测器包括具有与其相关联的第一阈值电压的第一晶体管。电阻元件耦合在第二节点和第三节点之间，电阻元件具有与之相关联的第一电阻值。该电路还包括具有耦合到第三节点并具有响应于第一控制信号产生第二控制信号的输出的反相器。逆变器包括具有与其相关联的第二阈值电压的第二晶体管，其低于第一阈值电压。电压电平检测器被配置为使得当电源电压小于第一电压时，第一控制信号基本上等于电源电压，并且当电源电压基本上等于或等于第一控制信号时，第一控制信号等于第二电压大于第一电压。第二电压小于逆变器的较低开关点，第一电压至少部分地基于第一阈值电压，复位信号是第二控制信号的函数。

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