专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060012406A1 Output buffer with selectable slew rate 有权
标题翻译：输出缓冲器，可选择转换速率
公开(公告)号：US20060012406A1
公开(公告)日：2006-01-19
申请号：US10891048
申请日：2004-07-15
申请人： Carol Huber , John Kriz , Brian Lacey , Bernard Morris
发明人： Carol Huber , John Kriz , Brian Lacey , Bernard Morris
IPC分类号： H03B1/00
CPC分类号： H03K17/163
摘要： A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.
摘要翻译：用于具有可调节转换速率控制的集成电路的缓冲器设计，但与具有压摆率控制的常规缓冲器相比，制造空间要小得多。将新的压摆率控制电路设计添加到互补金属氧化物半导体CMOS缓冲器中以在缓冲器中实现转换速率控制（例如，在高转换速率和低压摆率之间进行选择）。新的压摆率控制电路需要明显较少的制造空间，并且当应用于给定集成电路中的每个缓冲器（例如可沿着集成电路的周边放置的输入/输出缓冲器）时，节省的成本是非同寻常的。

2. 发明申请

US20060066381A1 Voltage level translator circuit with feedback 审中-公开
标题翻译：具有反馈电压电平转换电路
公开(公告)号：US20060066381A1
公开(公告)日：2006-03-30
申请号：US10956000
申请日：2004-09-30
申请人： Dipankar Bhattacharya , John Kriz , Brian Lacey , Bruce McNeill , Bernard Morris
发明人： Dipankar Bhattacharya , John Kriz , Brian Lacey , Bruce McNeill , Bernard Morris
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/356008 , H03K17/223
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal and a latch circuit for storing a signal at an output of the latch circuit which is representative of a logical state of the input signal. The latch circuit includes an input coupled to the input stage. The voltage level translator circuit further includes a feedback circuit coupled between the input and the output of the latch circuit. The feedback circuit is operative to maintain a desired logic state of the voltage level translator circuit when the second voltage supply powers up before the first voltage supply. In this manner, the voltage level translator circuit is configured to provide an output signal having a predictable logic state over a wide variation of PVT conditions and/or voltage supply ramp rates.
摘要翻译：用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级和用于在锁存电路的输出端存储信号的锁存电路其代表输入信号的逻辑状态。锁存电路包括耦合到输入级的输入端。电压电平转换器电路还包括耦合在锁存电路的输入和输出之间的反馈电路。当第二电压源在第一电压供应之前加电时，反馈电路可操作以保持电压电平转换器电路的期望逻辑状态。以这种方式，电压电平转换器电路被配置为在PVT条件和/或电压提供斜坡率的宽泛变化上提供具有可预测逻辑状态的输出信号。

3. 发明申请

US20070019348A1 Buffer circuit with enhanced overvoltage protection 有权
标题翻译：具有增强型过压保护功能的缓冲电路
公开(公告)号：US20070019348A1
公开(公告)日：2007-01-25
申请号：US11169139
申请日：2005-06-28
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
IPC分类号： H02H9/04
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A buffer circuit having enhanced overvoltage protection includes core buffer circuitry couplable to a first voltage source having a first voltage level. The core buffer circuitry is configured to receive a first signal and to generate a second signal which is a function of the first signal. The buffer circuit further includes a protection circuit coupled between the core buffer circuitry and a signal pad. The protection circuit is operative: (i) to clamp the first signal to about the first voltage level when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level.
摘要翻译：具有增强的过电压保护的缓冲电路包括可耦合到具有第一电压电平的第一电压源的核心缓冲电路。核心缓冲器电路被配置为接收第一信号并产生作为第一信号的函数的第二信号。缓冲电路还包括耦合在核心缓冲器电路和信号焊盘之间的保护电路。保护电路是可操作的：（i）当在信号焊盘处接收的第三信号超过第一电压电平达到第一量值时，将第一信号钳位到约第一电压电平; 和（ii）当第三信号小于或基本上等于第一电压电平时，产生基本上等于第三信号的第一信号。

4. 发明申请

US20060001449A1 Voltage level translator circuit 有权
公开(公告)号：US20060001449A1
公开(公告)日：2006-01-05
申请号：US10881192
申请日：2004-06-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Antonio Marques , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Antonio Marques , Bernard Morris
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for receiving the input signal. The input stage includes at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logical state of the input signal. The latch circuit includes at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp is operatively connected between the input stage and the latch circuit, the voltage clamp being configured to limit a voltage across the input stage based, at least in part, on a control signal presented thereto. The voltage level translator circuit includes a reference generator circuit for generating the control signal, a steady state value of the control signal being substantially equal to the first voltage level. The reference generator circuit is configured to adjust a voltage level of the control signal in response to the input signal.

5. 发明申请

US20070229157A1 Circuit having enhanced input signal range 有权
标题翻译：电路具有增强的输入信号范围
公开(公告)号：US20070229157A1
公开(公告)日：2007-10-04
申请号：US11393171
申请日：2006-03-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F2200/513 , H03F2200/78 , H03F2203/45314 , H03F2203/45361 , H03F2203/45552 , H03F2203/45684
摘要： A circuit having an enhanced input signal range includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference between the first and second signals. The differential amplifier includes an input stage having at least first and second transistors operative to receive the first and second signals, respectively, each of the first and second transistors having a first threshold voltage associated therewith, and a load including at least third and fourth transistors having a second threshold voltage associated therewith, the first threshold voltage being greater than the second threshold voltage. The circuit further includes an output stage coupled to the differential amplifier and being operative to receive the difference signal and to generate an output signal of the circuit, the output signal being indicative of the difference signal and being referenced to the first voltage. The circuit is configured to accept the first and second signals having a voltage swing which is potentially greater than a supply voltage of the circuit.
摘要翻译：具有增强的输入信号范围的电路包括差分放大器，其可操作以接收至少第一和第二信号并放大第一和第二信号之间的差。差分放大器在其输出处产生差分信号，其作为第一和第二信号之间的差异的函数。差分放大器包括具有至少第一和第二晶体管的输入级，其中第一和第二晶体管分别用于接收第一和第二信号，第一和第二晶体管中的每一个具有与之相关联的第一阈值电压，并且负载包括至少第三和第四晶体管具有与其相关联的第二阈值电压，所述第一阈值电压大于所述第二阈值电压。电路还包括耦合到差分放大器的输出级，并且可操作以接收差分信号并产生电路的输出信号，输出信号指示差分信号并参考第一电压。电路被配置为接受具有潜在地大于电路的电源电压的电压摆幅的第一和第二信号。

6. 发明申请

US20060220684A1 Buffer circuit with current limiting 失效
标题翻译：具有限流功能的缓冲电路
公开(公告)号：US20060220684A1
公开(公告)日：2006-10-05
申请号：US11094974
申请日：2005-03-31
申请人： Samuel Khoo , John Kriz , Bernard Morris
发明人： Samuel Khoo , John Kriz , Bernard Morris
IPC分类号： H03K19/094
CPC分类号： H03K19/018507 , H03K19/00315
摘要： A buffer circuit is configured to generate an output signal which is a function of an input signal received by the buffer circuit, the buffer circuit being selectively operative in one of at least two modes in response to a control signal. In a first mode, the buffer circuit is configured to provide a low output impedance, characteristic of a digital buffer. In a second mode, the buffer circuit is configured to limit an output current of the buffer circuit. The control signal is indicative of a level of the output signal of the buffer circuit.
摘要翻译：缓冲电路被配置为产生作为由缓冲电路接收的输入信号的函数的输出信号，缓冲电路响应于控制信号选择性地以至少两种模式之一操作。在第一模式中，缓冲电路被配置为提供数字缓冲器的特性的低输出阻抗。在第二模式中，缓冲电路被配置为限制缓冲电路的输出电流。控制信号表示缓冲电路的输出信号的电平。

7. 发明申请

US20060092589A1 Electrostatic discharge protection in a semiconductor device 有权
公开(公告)号：US20060092589A1
公开(公告)日：2006-05-04
申请号：US10977881
申请日：2004-10-29
申请人： Dipankar Bhattacharya , John Kriz , Bernard Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , John Kriz , Bernard Morris , Yehuda Smooha
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An ESD protection circuit for protecting a circuit from an ESD event occurring between a first voltage supply node and a second voltage supply node associated with the circuit to be protected includes an MOS device having a gate terminal, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal is connected to the first voltage supply node and the second source/drain terminal is connected to the second voltage supply node. The ESD protection circuit further includes a trigger circuit coupled to the gate terminal of the MOS device. The trigger circuit is configured to generate a control signal at the gate terminal of the MOS device for activating the MOS device during the ESD event. At least a portion of the trigger circuit is formed in a floating well which becomes biased to a voltage that is substantially equal to a first voltage when the first voltage is supplied to the first voltage supply node or to a second voltage when the second voltage is applied to the second voltage supply node, whichever voltage is greater.

8. 发明申请

US20070115030A1 Differential buffer circuit with reduced output common mode variation 失效
标题翻译：差分缓冲电路具有降低的输出共模变化
公开(公告)号：US20070115030A1
公开(公告)日：2007-05-24
申请号：US11285800
申请日：2005-11-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
IPC分类号： H03K19/094
CPC分类号： H04L25/0276
摘要： A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal. The buffer circuit further includes a common mode detection circuit and a common mode control circuit. The common mode detection circuit is operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage. The common mode control circuit includes a first terminal connected to the current source and a second terminal connected to the current sink. The common mode control circuit is operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.
摘要翻译：差分缓冲电路包括电流源，电流吸收器和连接到第一节点处的电流源并在第二节点处连接到电流宿的开关电路。开关电路可操作以响应于至少第一控制信号选择性地控制流过缓冲电路的差分输出的电流的方向。缓冲电路还包括共模检测电路和共模控制电路。共模检测电路用于检测缓冲电路的输出共模电压，并产生表示输出共模电压的第二控制信号。共模控制电路包括连接到电流源的第一端子和连接到电流阱的第二端子。共模控制电路用于根据第二控制信号有选择地控制缓冲电路的输出共模电压。

9. 发明申请

US20060192587A1 Self-bypassing voltage level translator circuit 有权
公开(公告)号：US20060192587A1
公开(公告)日：2006-08-31
申请号：US11065785
申请日：2005-02-25
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
IPC分类号： H03K19/0175
CPC分类号： H03K3/012 , H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.

10. 发明申请

US20060170461A1 Comparator circuit having reduced pulse width distortion 失效
标题翻译：比较器电路具有减小的脉冲宽度失真
公开(公告)号：US20060170461A1
公开(公告)日：2006-08-03
申请号：US11046995
申请日：2005-01-31
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris
IPC分类号： H03K5/22
CPC分类号： H03K5/2481 , H03K5/12
摘要： A comparator circuit having reduced pulse width distortion includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference between the first and second signals. An output stage is included in the comparator circuit for receiving the difference signal and for generating an output signal of the comparator circuit, the output signal being representative of the difference signal, the output stage having a switching point associated therewith. The comparator circuit further includes a voltage source coupled to the output of the differential amplifier. The voltage source is operative to generate a reference signal for establishing a common-mode voltage of the difference signal generated by the differential amplifier. The reference signal is substantially centered about the switching point of the output stage and substantially tracks the switching point over variations in process, voltage and/or temperature conditions to which the comparator circuit is subjected.
摘要翻译：具有减小的脉冲宽度失真的比较器电路包括差分放大器，其操作以接收至少第一和第二信号并且放大第一和第二信号之间的差。差分放大器在其输出处产生差分信号，其作为第一和第二信号之间的差异的函数。输出级包括在比较器电路中，用于接收差分信号并产生比较器电路的输出信号，该输出信号代表差分信号，输出级具有与之相关的切换点。比较器电路还包括耦合到差分放大器的输出的电压源。电压源用于产生用于建立由差分放大器产生的差分信号的共模电压的参考信号。参考信号基本上以输出级的切换点为中心，并且基本上跟踪比较器电路所经受的过程，电压和/或温度条件变化的切换点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式