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11. 发明申请

US20070046338A1 Buffer circuit with multiple voltage range 失效
标题翻译：具有多电压范围的缓冲电路
公开(公告)号：US20070046338A1
公开(公告)日：2007-03-01
申请号：US11215663
申请日：2005-08-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
IPC分类号： H03B1/00
CPC分类号： H03K19/018585 , H03K19/018521 , H03K19/018592
摘要： A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of the first buffer connects to an external pad of the buffer circuit, and an output of the second buffer connects to the pad via the isolation circuit. The buffer circuit is selectively operative in at least a first mode or a second mode in response to at least a first control signal. The isolation circuit is operative in the first mode to substantially isolate the second buffer from the external pad and is operative in the second mode to connect the output of the second buffer to the external pad.
摘要翻译：在多个电源电压电平下工作的缓冲电路包括第一和第二缓冲器，第一缓冲器被配置为与第一电压源一起操作，第二缓冲器与第二电压源一起工作。缓冲电路还包括可控隔离电路。第一缓冲器的输出连接到缓冲电路的外部焊盘，第二缓冲器的输出经由隔离电路连接到焊盘。响应于至少第一控制信号，缓冲器电路以至少第一模式或第二模式选择性地工作。隔离电路在第一模式下工作，以将第二缓冲器与外部焊盘基本隔离，并且在第二模式下工作，以将第二缓冲器的输出连接到外部焊盘。

12. 发明申请

US20060170462A1 RELIABILITY COMPARATOR WITH HYSTERESIS 有权
标题翻译：可靠性比较器与HYSTERESIS
公开(公告)号：US20060170462A1
公开(公告)日：2006-08-03
申请号：US11047388
申请日：2005-01-31
申请人： Dipankar Bhattacharya , John Kriz , Bernard Morris , William Wilson
发明人： Dipankar Bhattacharya , John Kriz , Bernard Morris , William Wilson
IPC分类号： H03K5/22
CPC分类号： H03K3/02337 , H03K3/3565
摘要： A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal. A hysteresis circuit is included in the comparator circuit for selectively controlling a switching threshold of the comparator, relative to the input signal, as a function of the output signal of the comparator. The comparator circuit includes a voltage clamp operative to limit a voltage applied to one or more devices in the control circuit, the comparator, and/or the hysteresis circuit to less than the second voltage.
摘要翻译：比较器电路包括连接到提供第一电压的第一源的参考发生器。参考发生器用于产生参考信号并且包括响应于第一控制信号选择性地以至少第一模式或第二模式操作的控制电路，其中在第一模式中不产生参考信号，并且在第二模式，参考发生器用于产生参考信号。比较器电路还包括连接到提供第二电压的第二源的比较器，第二电压小于第一电压。比较器用于接收参考信号和输入信号，并且产生作为输入信号和参考信号之间的比较的函数的输出信号。比较器电路中包括滞后电路，用于根据比较器的输出信号选择性地控制比较器相对于输入信号的切换阈值。比较器电路包括电压钳位器，用于将施加到控制电路，比较器和/或滞后电路中的一个或多个器件的电压限制为小于第二电压。

13. 发明申请

US20060145749A1 Bias circuit having reduced power-up delay 审中-公开
标题翻译：偏置电路具有降低的上电延迟
公开(公告)号：US20060145749A1
公开(公告)日：2006-07-06
申请号：US11026426
申请日：2004-12-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
IPC分类号： G05F1/10
CPC分类号： G05F3/205
摘要： A bias circuit includes a reference generator for generating a bias signal at an output of the reference generator. The reference generator is selectively operable a first mode or a second mode in response to a first control signal applied to the reference generator, wherein in the first mode of operation, the reference generator is disabled, and in the second mode of operation, the reference generator is operative to generate the bias signal. The bias circuit further includes a shunt circuit connected to the reference generator. The shunt circuit is configured to provide a source of current to assist in charging the output of the reference generator to a quiescent operating level during the second mode of operation. The shunt circuit, in response to a second control signal applied thereto, is operable for a selected period time after the reference generator transitions from the first mode of operation to the second mode of operation.
摘要翻译：偏置电路包括用于在参考发生器的输出处产生偏置信号的参考发生器。参考发生器响应于施加到参考发生器的第一控制信号而选择性地操作第一模式或第二模式，其中在第一操作模式中，参考发生器被禁用，并且在第二操作模式中，发生器用于产生偏置信号。偏置电路还包括连接到参考发生器的分流电路。分流电路被配置为提供电流源以帮助在第二操作模式期间将参考发生器的输出充电到静止工作电平。分流电路响应于施加到其上的第二控制信号可在参考发生器从第一操作模式转换到第二操作模式之后的所选时段内操作。

14. 发明申请

US20060103427A1 Overvoltage tolerant input buffer 有权
公开(公告)号：US20060103427A1
公开(公告)日：2006-05-18
申请号：US10988103
申请日：2004-11-12
申请人： Dipankar Bhattacharya , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , John Kriz , Bernard Morris
IPC分类号： H03K19/094
CPC分类号： H03K19/00315
摘要： When a P-channel pass gate transistor is added in parallel to an N-channel pass gate, the resulting circuit improves overvoltage tolerance of an input buffer. A simple bias circuit including two small transistors controls a gate of this P-channel pass gate transistor in such a way that it is turned OFF when an overvoltage is applied, but turned ON when a normal voltage is applied. Another embodiment has two N-channel devices (M12, M13) coupled in series with each other and one of the N-channel devices (M13) being configured in a “turned off” position, by coupling the source and gate terminals to a ground voltage (VSS) and providing the supply voltage (VDD) at the gate terminal of another N-channel device (M12), whereby the device M12 protects the device M13 from overvoltage.

15. 发明申请

US20050134364A1 Reference compensation circuit 有权
标题翻译：参考补偿电路
公开(公告)号：US20050134364A1
公开(公告)日：2005-06-23
申请号：US10744801
申请日：2003-12-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Jeffrey Nagy , Stefan Siegel
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Jeffrey Nagy , Stefan Siegel
IPC分类号： G05F3/02 , G05F3/24
CPC分类号： G05F3/245 , G05F3/247
摘要： A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit. The control circuit is operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively.
摘要翻译：补偿电路包括参考电路，该参考电路包括参考NMOS器件和参考PMOS器件。参考电路可操作以产生第一参考信号和第二参考信号，第一参考信号是参考NMOS器件的处理特性，电压特性和温度特性中的至少一个的函数，第二参考信号信号是参考PMOS器件的工艺特性，电压特性和温度特性中的至少一个的函数。补偿电路还包括连接到参考电路的控制电路。控制电路可操作以接收第一和第二参考信号并产生一个或多个输出信号，用于补偿至少一个NMOS器件的工艺特性，电压特性和温度特性中的至少一个的变化，并且在响应于第一和第二参考信号，要补偿的电路中的至少一个PMOS器件可连接到控制电路。

16. 发明申请

US20060012406A1 Output buffer with selectable slew rate 有权
标题翻译：输出缓冲器，可选择转换速率
公开(公告)号：US20060012406A1
公开(公告)日：2006-01-19
申请号：US10891048
申请日：2004-07-15
申请人： Carol Huber , John Kriz , Brian Lacey , Bernard Morris
发明人： Carol Huber , John Kriz , Brian Lacey , Bernard Morris
IPC分类号： H03B1/00
CPC分类号： H03K17/163
摘要： A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.
摘要翻译：用于具有可调节转换速率控制的集成电路的缓冲器设计，但与具有压摆率控制的常规缓冲器相比，制造空间要小得多。将新的压摆率控制电路设计添加到互补金属氧化物半导体CMOS缓冲器中以在缓冲器中实现转换速率控制（例如，在高转换速率和低压摆率之间进行选择）。新的压摆率控制电路需要明显较少的制造空间，并且当应用于给定集成电路中的每个缓冲器（例如可沿着集成电路的周边放置的输入/输出缓冲器）时，节省的成本是非同寻常的。

17. 发明申请

US20050270065A1 Coms buffer having higher and lower voltage operation 审中-公开
标题翻译： Coms缓冲器具有更高和更低的电压操作
公开(公告)号：US20050270065A1
公开(公告)日：2005-12-08
申请号：US10859211
申请日：2004-06-03
申请人： Dipankar Bhattacharya , Brijendra Dobriyal , Bernard Morris
发明人： Dipankar Bhattacharya , Brijendra Dobriyal , Bernard Morris
IPC分类号： H03K3/00 , H03K17/0412 , H03K17/06 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018585 , H03K17/04123 , H03K17/063 , H03K19/018521
摘要： A buffer design for an integrated circuit that not only recognizes, but improves upon the skew problem as described above that is particularly problematic in cases where the output buffer supply voltage is particularly close or the same as the voltage of the signals coming from the core of an IC. Translator-up circuits associated with output buffers are implemented in parallel with respective selective bypass circuits, allowing the translator-up circuit to be inserted into or removed from a signal path based on the voltage level of a signal received from the inner core and the voltage level required by the output buffer. When the voltage level of the “higher” voltage side is equal to the “lower” voltage signal level, the translator-up circuits are bypassed through selection by a selective bypass circuit. Thus, a selective bypass circuit is implemented together with a translator-up circuit to eliminate large signal skew, and to generally speed up circuit performance.
摘要翻译：一种用于集成电路的缓冲器设计，其不仅识别但改进了如上所述的偏斜问题，在输出缓冲器电源电压特别接近或相同于来自芯的信号的电压的情况下，这是特别有问题的一个IC 与输出缓冲器相关联的转换电路与相应的选择旁路电路并行实现，允许转换器升高电路基于从内核接收的信号的电压电平和电压插入或从信号路径中去除输出缓冲区所需的电平。当“较高”电压侧的电压电平等于“较低”电压信号电平时，通过选择旁路电路的选择旁路转换器电路。因此，选择性旁路电路与转换器升压电路一起实现，以消除大的信号偏移，并且通常加速电路性能。

18. 发明申请

US20060220684A1 Buffer circuit with current limiting 失效
标题翻译：具有限流功能的缓冲电路
公开(公告)号：US20060220684A1
公开(公告)日：2006-10-05
申请号：US11094974
申请日：2005-03-31
申请人： Samuel Khoo , John Kriz , Bernard Morris
发明人： Samuel Khoo , John Kriz , Bernard Morris
IPC分类号： H03K19/094
CPC分类号： H03K19/018507 , H03K19/00315
摘要： A buffer circuit is configured to generate an output signal which is a function of an input signal received by the buffer circuit, the buffer circuit being selectively operative in one of at least two modes in response to a control signal. In a first mode, the buffer circuit is configured to provide a low output impedance, characteristic of a digital buffer. In a second mode, the buffer circuit is configured to limit an output current of the buffer circuit. The control signal is indicative of a level of the output signal of the buffer circuit.
摘要翻译：缓冲电路被配置为产生作为由缓冲电路接收的输入信号的函数的输出信号，缓冲电路响应于控制信号选择性地以至少两种模式之一操作。在第一模式中，缓冲电路被配置为提供数字缓冲器的特性的低输出阻抗。在第二模式中，缓冲电路被配置为限制缓冲电路的输出电流。控制信号表示缓冲电路的输出信号的电平。

19. 发明申请

US20060044016A1 Integrated circuit with signal skew adjusting cell selected from cell library 审中-公开
公开(公告)号：US20060044016A1
公开(公告)日：2006-03-02
申请号：US10925185
申请日：2004-08-24
申请人： Martin Gasper , Bernard Morris
发明人： Martin Gasper , Bernard Morris
IPC分类号： H03K19/00
CPC分类号： G06F17/5045 , H03K5/1565 , H03K19/00323
摘要： An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal in the digital circuitry of the integrated circuit to a desired amount. The digital logic cell and the skew adjusting cell are selected from a cell library.

20. 发明申请

US20070256047A1 Integrated Circuit with Signal Skew Adjusting Cell Selected from Cell Library 失效
标题翻译：具有从单元库选择的信号偏移调整单元的集成电路
公开(公告)号：US20070256047A1
公开(公告)日：2007-11-01
申请号：US11774022
申请日：2007-07-06
申请人： Martin Gasper, Jr. , Bernard Morris
发明人： Martin Gasper, Jr. , Bernard Morris
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , H03K5/1565 , H03K19/00323
摘要： An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal in the digital circuitry of the integrated circuit to a desired amount. The digital logic cell and the skew adjusting cell are selected from a cell library.
摘要翻译：集成电路包括具有至少一个数字逻辑单元和至少一个偏斜调整单元的数字电路。偏斜调整单元被配置为将集成电路的数字电路中的信号的偏斜调整到期望的量。从单元库中选择数字逻辑单元和偏斜调整单元。

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