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11. 发明授权

US6010963A Global planarization using SOG and CMP 失效
标题翻译：使用SOG和CMP的全局平面化
公开(公告)号：US6010963A
公开(公告)日：2000-01-04
申请号：US567504
申请日：1995-12-05
申请人： Derryl D. J. Allman , Kenneth P. Fuchs
发明人： Derryl D. J. Allman , Kenneth P. Fuchs
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/20
CPC分类号： H01L21/76819 , H01L21/31053 , H01L21/31055 , H01L21/316
摘要： A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.
摘要翻译：在化学金属抛光（CMP）操作之前，使用旋涂玻璃（SOG）的半导体器件的表面平坦化的方法和蚀刻操作来去除SOG的高部分。 SOG在蚀刻前烘烤和固化。根据需要可以采用附加的SOG层和蚀刻操作。在SOG层上沉积厚的封装氧化物层。对于由金属线引起的表面凹凸，绝缘层可能沉积在SOG之前的表面上。在附加金属线要沉积在表面上的情况下，在CMP操作之后沉积附加的绝缘层。在由铝制成的金属线的情况下，还提供用于防止金属线上的小丘形成。

12. 发明授权

US5312512A Global planarization using SOG and CMP 失效
标题翻译：使用SOG和CMP的全局平面化
公开(公告)号：US5312512A
公开(公告)日：1994-05-17
申请号：US965309
申请日：1992-10-23
申请人： Derryl D. J. Allman , Kenneth P. Fuchs
发明人： Derryl D. J. Allman , Kenneth P. Fuchs
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/306 , H01L21/465
CPC分类号： H01L21/76819 , H01L21/31053 , H01L21/31055 , H01L21/316
摘要： A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.
摘要翻译：在化学金属抛光（CMP）操作之前，使用旋涂玻璃（SOG）的半导体器件的表面平坦化的方法和蚀刻操作来去除SOG的高部分。 SOG在蚀刻前烘烤和固化。根据需要可以采用附加的SOG层和蚀刻操作。在SOG层上沉积厚的封装氧化物层。对于由金属线引起的表面凹凸，绝缘层可能沉积在SOG之前的表面上。在附加金属线要沉积在表面上的情况下，在CMP操作之后沉积附加的绝缘层。在由铝制成的金属线的情况下，还提供用于防止金属线上的小丘形成。

13. 发明申请

US20080132065A1 METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN 失效
标题翻译：在集成电路设计中从VIAS重新排列无声扩散的方法
公开(公告)号：US20080132065A1
公开(公告)日：2008-06-05
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

14. 发明授权

US06583026B1 Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure 有权
标题翻译：在集成电路结构上形成低k碳掺杂氧化硅介电材料的工艺
公开(公告)号：US06583026B1
公开(公告)日：2003-06-24
申请号：US09872058
申请日：2001-05-31
申请人： Derryl D. J. Allman , Ponce Saopraseuth , Hemanshu D. Bhatt
发明人： Derryl D. J. Allman , Ponce Saopraseuth , Hemanshu D. Bhatt
IPC分类号： H01L2176
CPC分类号： H01L21/02126 , C23C16/401 , H01L21/02211 , H01L21/0228 , H01L21/02304 , H01L21/0234 , H01L21/31633
摘要： A process for forming a low k carbon-doped silicon oxide dielectric material (lkc-dsodm) on an integrated circuit structure is characterized by improved planarity and good gap fill in high aspect ratio regions of the integrated circuit structure, as well as improved film strength and adherence, and less byproducts trapped in the film. The process comprises: depositing a plurality of layers of lkc-dsodm on an integrated circuit structure in a reactor; and pausing after depositing each layer of lkc-dsodm and before depositing a further layer of lkc-dsodm. The process can further include first forming a base or barrier layer of a silicon-rich and nitrogen-rich dielectric material over the integrated circuit structure, plasma etching the upper surface of the barrier layer to facilitate adhesion of the subsequently deposited lkc-dsodm to the barrier layer, and then, before depositing the first layer of lkc-dsodm, cooling the etched barrier layer down to within 10° C. or less of the subsequent deposition temperature used for formation of the film of lkc-dsodm. In another aspect of the invention the pausing step further includes, before deposition of the next layer of lkc-dsodm, flowing a source of non-reactive gas over the surface of the newly deposited layer of lkc-dsodm to facilitate outgassing and removal of byproducts resulting from the preceding formation and deposition of lkc-dsodm.
摘要翻译：在集成电路结构上形成低k碳掺杂氧化硅电介质材料（lkc-dsodm）的方法的特征在于集成电路结构的高纵横比区域中的平坦度和良好的间隙填充，以及改进的膜强度和坚持，更少的副产品被困在电影中。该方法包括：在反应器中的集成电路结构上沉积多层lkc-dsodm; 并且在沉积每层lkc-dsodm之后并在沉积另外一层lkc-dsodm之前暂停。该方法还可以包括首先在集成电路结构上形成富硅和富氮介电材料的基底或阻挡层，等离子体蚀刻阻挡层的上表面，以便于随后沉积的lkc-dsodm粘附到然后在沉积第一层lkc-dsodm之前，将蚀刻的阻挡层冷却到用于形成lkc-dsodm膜的后续沉积温度的10℃以内。在本发明的另一方面，暂停步骤还包括在沉积下一层lkc-dsodm之前，将非反应性气体源流过新沉积的lkc-dsodm层的表面以便于除气和除去副产物由于以前的lkc-dsodm的形成和沉积而产生。

15. 发明授权

US06504202B1 Interconnect-embedded metal-insulator-metal capacitor 有权
标题翻译：互连嵌入式金属 - 绝缘体 - 金属电容器
公开(公告)号：US06504202B1
公开(公告)日：2003-01-07
申请号：US09496971
申请日：2000-02-02
申请人： Derryl D. J. Allman , Kenneth Fuchs
发明人： Derryl D. J. Allman , Kenneth Fuchs
IPC分类号： H01L2976
CPC分类号： H01L28/40 , H01L21/768 , H01L28/75
摘要： A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.
摘要翻译：金属 - 绝缘体 - 金属电容器嵌入在集成电路（IC）的互连层中。互连层具有空腔，并且电容器形成在空腔中，电容器的一个板与互连层的导电层成一体，因此电容器板与互连层电连通。互连层具有多个导电层，包括在制造IC期间在特定温度下经受变形的诸如铝的层，并且空腔延伸穿过该层。互连层的剩余导电层限定电容器板中的一个，并且在腔内形成介电层和另一电容器板。通过大致相同长度的互连电连接到顶板并且通过互连层连接到底板。

16. 发明授权

US6136662A Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same 有权
标题翻译：具有层间对准标记的半导体晶片及其制造方法
公开(公告)号：US6136662A
公开(公告)日：2000-10-24
申请号：US311253
申请日：1999-05-13
申请人： Derryl D. J. Allman , Curtis C. Hainds , Charles W. Jurgensen , Brian R. Lee
发明人： Derryl D. J. Allman , Curtis C. Hainds , Charles W. Jurgensen , Brian R. Lee
IPC分类号： G03F9/00 , H01L23/544 , H01L21/76 , H01L21/302 , H01L21/4763
CPC分类号： G03F9/708 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.
摘要翻译：在半导体晶片中形成层间对准标记的方法包括在与半导体晶片相关联的衬底上沉积第一导体层的步骤。该方法还包括在第一导体层中制造多个对准沟槽的步骤。此外，该方法包括在第一导体层上沉积第一绝缘体层以填充对准沟槽的数量的步骤。此外，该方法包括以下步骤：从对准沟槽的数量去除与第一绝缘体层相关联的材料，使得第一导体层的上表面和第一绝缘体层的上表面限定第一对准步骤特征，其具有一个预定的高度。该方法还包括在去除步骤之后在半导体晶片上沉积第二导体层的步骤。还公开了半导体晶片。

17. 发明授权

US5302198A Coating solution for forming glassy layers 失效
标题翻译：用于形成玻璃层的涂层溶液
公开(公告)号：US5302198A
公开(公告)日：1994-04-12
申请号：US582570
申请日：1990-09-14
申请人： Derryl D. J. Allman
发明人： Derryl D. J. Allman
IPC分类号： G03F1/08 , G03F7/09 , H01L21/027 , H01L23/532 , C09K3/00 , C08G77/00
CPC分类号： H01L23/5329 , G03F7/091 , G03F7/094 , H01L21/0276 , H01L2924/0002
摘要： There is disclosed a method for producing a spin-on glass composition with a high carbon content for use as coating layers on substrates such as semiconductor silicon wafers. Also provided are spin-on glass compositions with polyorganosiloxanes having at least 30 wt.% carbon. These spin-on glass compositions show improved resistance to O.sub.2 concentration variations during etching and have an extended shelf-life of more than one year. Methods of using these spin-on glass compositions and semiconductor products produced therefrom are also provided.
摘要翻译：公开了一种用于生产具有高碳含量的旋涂玻璃组合物的方法，用作诸如半导体硅晶片的基底上的涂层。还提供了具有至少30重量％碳的聚有机硅氧烷的旋涂玻璃组合物。这些旋涂玻璃组合物在蚀刻期间显示出改善的耐O2浓度变化的耐受性，并且具有超过一年的延长的保存期限。还提供了使用这些旋涂玻璃组合物和由其制备的半导体产品的方法。

18. 发明授权

US07598127B2 Nanotube fuse structure 有权
标题翻译：纳米管保险丝结构
公开(公告)号：US07598127B2
公开(公告)日：2009-10-06
申请号：US11284503
申请日：2005-11-22
申请人： Bruce J. Whitefield , Derryl D. J. Allman , Thomas Rueckes , Claude L. Bertin
发明人： Bruce J. Whitefield , Derryl D. J. Allman , Thomas Rueckes , Claude L. Bertin
IPC分类号： H01L21/86
CPC分类号： H01L23/5258 , H01L23/5256 , H01L2924/0002 , Y10S977/742 , H01L2924/00
摘要： A method of forming a carbon nanotube fuse by depositing a carbon nanotube layer, then depositing a cap layer directly over the carbon nanotube layer. The cap layer is formed of a material that has an insufficient amount of oxygen to significantly oxidize the carbon nanotube layer under operating conditions, and is otherwise sufficiently robust to protect the carbon nanotube layer from oxygen and plasmas. A photoresist layer is formed over the cap layer, and the photoresist layer is patterned to define a desired size of fuse. Both the cap layer and the carbon nanotube layer are completely etched, without removing the photoresist layer, to define the fuse having two ends in the carbon nanotube layer. Just the cap layer is etched, without removing the photoresist layer, so as to reduce the cap layer by a desired amount at the edges of the cap layer under the photoresist layer, without damaging the carbon nanotube layer. The photoresist layer is removed, and electrically conductive contacts are formed on each of the two ends of the fuse.
摘要翻译：通过沉积碳纳米管层形成碳纳米管熔丝，然后在碳纳米管层上直接沉积覆盖层的方法。盖层由具有不足量的氧的材料形成，以在操作条件下显着地氧化碳纳米管层，否则足够坚固以保护碳纳米管层免受氧气和等离子体的影响。在盖层上形成光致抗蚀剂层，并且将光致抗蚀剂层图案化以限定所需尺寸的熔丝。完全蚀刻盖层和碳纳米管层，而不去除光致抗蚀剂层，以限定在碳纳米管层中具有两端的熔丝。只是盖层被蚀刻，而不去除光致抗蚀剂层，以便在光致抗蚀剂层下的盖层的边缘处将盖层减少所需量，而不损害碳纳米管层。去除光致抗蚀剂层，并且在熔丝的两端的每一端上形成导电触点。

19. 发明授权

US07582566B2 Method for redirecting void diffusion away from vias in an integrated circuit design 失效
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法
公开(公告)号：US07582566B2
公开(公告)日：2009-09-01
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/311
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

20. 发明授权

US07253497B2 Integrated circuit with inductor having horizontal magnetic flux lines 有权
标题翻译：具有水平磁通线的电感的集成电路
公开(公告)号：US07253497B2
公开(公告)日：2007-08-07
申请号：US10614307
申请日：2003-07-02
申请人： Hemanshu D. Bhatt , Jan Fure , Derryl D. J. Allman
发明人： Hemanshu D. Bhatt , Jan Fure , Derryl D. J. Allman
IPC分类号： H01L29/00
CPC分类号： H01L28/10 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.
摘要翻译：集成电路（IC）包括具有基本上平行于IC的大致水平面的磁通线的一个或多个电感器。电感器形成在由IC的绝缘层分离的多个导体层中。电感器的最大磁通密度的区域优选地位于IC边缘附近。另外，电感器可以优选地被分段。可以优选地通过接通和关断所选择的电感器或电感器段来控制全部电感。

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