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11. 发明授权

US06177807B1 High frequency valid data strobe 失效
标题翻译：高频有效数据选通
公开(公告)号：US06177807B1
公开(公告)日：2001-01-23
申请号：US09322465
申请日：1999-05-28
申请人： Claude L. Bertin , John A. Fifield , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
IPC分类号： G03K1716
CPC分类号： G06F13/4086 , H03K5/06 , H04L25/0298
摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.
摘要翻译：具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。具有递增可变长度的传输线短截线连接到控制线14的存储器控制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。

12. 发明授权

US6070262A Reconfigurable I/O DRAM 失效
标题翻译：可重配置I / O DRAM
公开(公告)号：US6070262A
公开(公告)日：2000-05-30
申请号：US833367
申请日：1997-04-04
申请人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
发明人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
IPC分类号： G06F11/10 , G06F12/00 , G11C7/10 , G11C29/00
CPC分类号： G11C7/1057 , G06F11/1044 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.
摘要翻译：动态随机存取存储器（DRAM）可由八（x8）或九（x9）配置。 DRAM具有9个数据输入/输出（I / O）。存储器阵列被分成两个或更多个子阵列，子阵列单元被布置成可寻址的行和列。当DRAM被配置为x8时，一个I / O保持在其高阻抗状态; DRAM的数据路径（阵列和第九个I / O之间）的九分之一被忽略; 并且整个阵列地址空间可用于通过八个I / O进行数据存储。当DRAM配置为x9时，所有9个I / O都有效; DRAM I / O路径被配置为通过第九个I / O提供第九位的阵列的一部分; 并且阵列地址空间减少了八分之一。所有9位可能来自公共子阵列。或者，子阵列可以配对，使得当DRAM被配置为x9时，在一个子阵列的七分之八中访问八个比特，其中第九比特在该对的另一个子阵列的八分之一中被访问。

13. 发明授权

US06812122B2 Method for forming a voltage programming element 有权
标题翻译：用于形成电压编程元件的方法
公开(公告)号：US06812122B2
公开(公告)日：2004-11-02
申请号：US10095889
申请日：2002-03-12
申请人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
发明人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
IPC分类号： H01L2144
CPC分类号： H01L21/763 , H01L23/5252 , H01L27/10861 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： Method for forming a first one time, voltage programmable logic element in a semiconductor substrate of first conductivity type, forming a first layer beneath a surface of the substrate, the first layer having a second conductivity type. A trench is formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench.
摘要翻译：用于形成第一导电类型的半导体衬底中的第一次电压可编程逻辑元件的方法，在所述衬底的表面下方形成第一层，所述第一层具有第二导电类型。沟槽通过表面形成并穿过第一层。沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。

14. 发明授权

US06567950B1 Dynamically replacing a failed chip 失效
标题翻译：动态更换故障芯片
公开(公告)号：US06567950B1
公开(公告)日：2003-05-20
申请号：US09302917
申请日：1999-04-30
申请人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg
发明人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg
IPC分类号： G11C2900
CPC分类号： G11C29/70 , G11C29/838
摘要： An improved chip sparing system and method of operation are provided in which a failed chip is detected even if there are multiple errors on a single chip and one or more spare chips are provided within the system; and in which spare chips or space chip I/Os are dynamically inserted into the system upon detection of a failed chip or chip I/O without the necessity of shutting down and rebooting the system or even without the necessity of re-initializing the memory.
摘要翻译：提供了一种改进的芯片保存系统和操作方法，其中即使在单个芯片上存在多个错误并且在系统内提供一个或多个备用芯片，也检测到故障芯片; 并且在检测到故障的芯片或芯片I / O时，备用芯片或空芯片I / O被动态地插入到系统中，而不需要关闭和重新启动系统，或者甚至不需要重新初始化存储器。

15. 发明授权

US06297531B2 High performance, low power vertical integrated CMOS devices 失效
标题翻译：高性能，低功耗的垂直集成CMOS器件
公开(公告)号：US06297531B2
公开(公告)日：2001-10-02
申请号：US09002399
申请日：1998-01-05
申请人： Michael D. Armacost , Claude L. Bertin , Erik L. Hedberg , Jack A. Mandelman
发明人： Michael D. Armacost , Claude L. Bertin , Erik L. Hedberg , Jack A. Mandelman
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L21/823885 , H01L21/84 , H01L27/1104 , H01L27/1203 , Y10S257/903
摘要： A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETS; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer. The SRAM cell may be radiation hardened by selectively thickening gate layers to increase storage node capacitance, providing high resistance cell wiring or by including a multi-layered gate oxide layer of NO or ONO, or by any combination thereof.
摘要翻译：可以是N型FET（NFET）或P型FET（PFET）的垂直场效应晶体管（FET）; 可以是两个或更多个NFET或两个或更多个PFETS的多器件垂直结构; 逻辑门包括至少一个垂直FET或至少一个多器件垂直; 包括至少一个垂直FET的静态随机存取存储器（SRAM）单元和阵列; 包括至少一个这样的SRAM单元的存储器阵列; 以及形成垂直FET结构的过程，垂直多器件（multi-FET）结构，逻辑门和SRAM单元。垂直FET是NPN或PNP的外延生长层叠堆叠，其中多晶硅栅极层的侧面与器件的沟道层相邻。多FET结构可以通过形成与相同沟道层相邻的两个或多个栅极的侧面，或者通过在相同的堆叠中形成多个通道层，例如PNPNP或NPNPN，每个具有其自己的栅极，即侧面的多晶硅栅极层。 SRAM单元可以通过选择性地增厚栅极层而辐射硬化，以增加存储节点电容，提供高电阻电池布线或者通过包括NO或ONO的多层栅极氧化物层或其任何组合。

16. 发明授权

US06388305B1 Electrically programmable antifuses and methods for forming the same 有权
标题翻译：电子可编程反熔丝及其形成方法
公开(公告)号：US06388305B1
公开(公告)日：2002-05-14
申请号：US09466495
申请日：1999-12-17
申请人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
发明人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
IPC分类号： H01L2900
CPC分类号： H01L21/763 , H01L23/5252 , H01L27/10861 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a first dielectric material lining the interior surface and a second dielectric material filling the lined trench. The second logic element further comprises a dielectric layer formed over a portion of the first layer and contacting the first dielectric material lining the trench at a merge location; and an electrode extending over a portion of both the dielectric layer and the filled trench. The second logic element is configured so that a predetermined voltage or higher applied between the electrode and the first layer causes a breakdown near the merge location.
摘要翻译：首先，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该第一导电类型的半导体衬底包括在衬底的表面下面的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。第二次，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该半导体衬底包括形成在衬底的表面中的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。沟槽包括内表面，衬在内表面的第一电介质材料和填充衬里沟槽的第二电介质材料。第二逻辑元件还包括形成在第一层的一部分上并且在合并位置处接触衬套在沟槽上的第一介电材料的电介质层; 以及在电介质层和填充沟槽的一部分上延伸的电极。第二逻辑元件被配置为使得施加在电极和第一层之间的预定电压或更高的电压导致合并位置附近的击穿。

17. 发明授权

US06178517B1 High bandwidth DRAM with low operating power modes 失效
标题翻译：具有低工作功率模式的高带宽DRAM
公开(公告)号：US06178517B1
公开(公告)日：2001-01-23
申请号：US09121933
申请日：1998-07-24
申请人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
发明人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.
摘要翻译：高带宽DRAM具有将DRAM连接到处理器的两个单独的总线网络。一个总线网络是高速（例如，500MHz）8：1或16：1多路复用I / O总线，第二个是较慢（例如，64位）总线。例如，高速总线用于需要快速访问DRAM存储器阵列中大量位的图形密集型应用。这当然会导致更高的功率需求。由于并非所有应用都需要在DRAM和处理器之间传输大量数据，所以为这些不太要求苛刻的应用程序提供较慢的总线，例如文字处理器，电子表格等。较慢的总线需要更少的功率来进行操作，因此导致省电模式，其中尤其有助于延长电池寿命。

18. 发明授权

US6137129A High performance direct coupled FET memory cell 失效
标题翻译：高性能直接耦合FET存储单元
公开(公告)号：US6137129A
公开(公告)日：2000-10-24
申请号：US2825
申请日：1998-01-05
申请人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
发明人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
IPC分类号： H01L21/8244 , H01L27/11 , H01L27/108 , H01L29/74 , H01L29/76
CPC分类号： H01L27/11 , Y10S257/903
摘要： A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO.sub.2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer. Second, the cell pass gates are formed on a pass gate or Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the preferred latch layer.
摘要翻译：一对直接耦合的场效应晶体管（FET），直接耦合FETS的锁存器，包括直接耦合FET的锁存器的静态随机存取存储器（SRAM）单元和形成直接耦合的FET结构的过程，锁存器和SRAM单元。可以是PFET，NFET或者其中之一的垂直FET是由栅极氧化物SiO 2分离的外延生长的NPN或PNP堆叠。每个设备的门是该对的另一个设备的源或漏极。优选实施例锁存器包括两对这样的直接耦合的垂直FET对，连接在一起以形成交叉耦合的反相器。通路栅极层结合到优选实施例锁存器的一个表面上以形成优选实施例SRAM单元的阵列。 SRAM单元可以包括一个或两个传递门。优选实施例SRAM过程具有三个主要步骤。首先，优选实施例的锁存器形成在硅晶片上的氧化物层中。第二，在传输门或输入/输出（I / O）层上形成单元传输门。第三，I / O层被粘合并连接到优选的锁存层。

19. 发明授权

US5896404A Programmable burst length DRAM 失效
标题翻译：可编程突发长度DRAM
公开(公告)号：US5896404A
公开(公告)日：1999-04-20
申请号：US833371
申请日：1997-04-04
申请人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
发明人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
IPC分类号： G06F12/16 , G06F11/10 , G11C7/10 , G11C11/401 , G11C29/42 , G11C29/00
CPC分类号： G06F11/1008 , G11C7/1018 , G06F11/1052
摘要： A Dynamic Random Access Memory (DRAM) with a burst length programmable as eight (8) or nine (9) bytes. The DRAM array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is programmed in Normal mode, the burst length is 8 and the entire array address space is available for data storage. When the DRAM is programmed for error checking (ECC mode), the burst length is nine and the array is reconfigured with part of the array providing the ninth byte. The DRAM's address space is reduced by one-eighth in ECC mode. Preferably, all nine locations are in the same page, with each page being divided into eight equal portions. In Normal mode all eight equal portions are data storage; and, in ECC mode, seven-eighths of the page is data storage, the remaining one eighth being assigned to check bit storage.
摘要翻译：具有可编程为八（8）或九（9）字节的突发长度的动态随机存取存储器（DRAM）。 DRAM阵列分为两个或更多个子阵列，子阵列单元以可寻址的行和列排列。当DRAM在正常模式下编程时，突发长度为8，整个阵列地址空间可用于数据存储。当DRAM被编程用于错误检查（ECC模式）时，突发长度为9，并且阵列被配置为提供第九个字节的阵列的一部分。在ECC模式下，DRAM的地址空间减少了八分之一。优选地，所有九个位置在同一页面中，每个页面被分成八个相等的部分。在正常模式下，所有八个相等的部分都是数据存储; 并且在ECC模式中，页面的七分之一是数据存储，剩下的八分之一被分配给校验位存储。

20. 发明授权

US06633055B2 Electronic fuse structure and method of manufacturing 有权
标题翻译：电子熔断器结构及制造方法
公开(公告)号：US06633055B2
公开(公告)日：2003-10-14
申请号：US09303509
申请日：1999-04-30
申请人： Claude L. Bertin , Erik L. Hedberg , Max G. Levy , Timothy D. Sullivan , William R. Tonti
发明人： Claude L. Bertin , Erik L. Hedberg , Max G. Levy , Timothy D. Sullivan , William R. Tonti
IPC分类号： H01L2974
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A gap conductor structure for an integrated electronic circuit that may function as an electronic fuse device or as a low capacitance inter level signal line is integrated as part of the semi-conductor chip wiring. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to melt a part of the conducting line. The presence of gaps, and hence, the fuses, are scalable and may be tailored to the capacity of currents they must carry with the characteristics of the fuses defined by a circuit designer. Furthermore, conducting structures completely or partially exposed in the air gap may function as low capacitance minimum delay transmission lines.
摘要翻译：作为半导体芯片布线的一部分，集成电子电路的可用作电子熔断器件或低电容级间信号线的间隙导体结构被集成。间隙导电结构包括一个或多个预定体积的气隙区域，其完全或部分地暴露IC中的层间导体层的长度。或者，气隙区域可以完全位于相应导体下方的电介质区域内并被绝缘体分隔开。当用作熔丝时，间隙区域用于降低远离导体的暴露部分的热导率，使得能够以较低的施加电压在导线中产生更高的热流，从而熔化导电线的一部分。间隙的存在以及保险丝的存在是可扩展的，并且可以根据电路设计者定义的保险丝的特性来适应其必须携带的电流的容量。此外，在气隙中完全或部分暴露的导电结构可用作低电容最小延迟传输线

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