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1. 发明授权

US6137129A High performance direct coupled FET memory cell 失效
标题翻译：高性能直接耦合FET存储单元
公开(公告)号：US6137129A
公开(公告)日：2000-10-24
申请号：US2825
申请日：1998-01-05
申请人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
发明人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
IPC分类号： H01L21/8244 , H01L27/11 , H01L27/108 , H01L29/74 , H01L29/76
CPC分类号： H01L27/11 , Y10S257/903
摘要： A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO.sub.2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer. Second, the cell pass gates are formed on a pass gate or Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the preferred latch layer.
摘要翻译：一对直接耦合的场效应晶体管（FET），直接耦合FETS的锁存器，包括直接耦合FET的锁存器的静态随机存取存储器（SRAM）单元和形成直接耦合的FET结构的过程，锁存器和SRAM单元。可以是PFET，NFET或者其中之一的垂直FET是由栅极氧化物SiO 2分离的外延生长的NPN或PNP堆叠。每个设备的门是该对的另一个设备的源或漏极。优选实施例锁存器包括两对这样的直接耦合的垂直FET对，连接在一起以形成交叉耦合的反相器。通路栅极层结合到优选实施例锁存器的一个表面上以形成优选实施例SRAM单元的阵列。 SRAM单元可以包括一个或两个传递门。优选实施例SRAM过程具有三个主要步骤。首先，优选实施例的锁存器形成在硅晶片上的氧化物层中。第二，在传输门或输入/输出（I / O）层上形成单元传输门。第三，I / O层被粘合并连接到优选的锁存层。

2. 发明授权

US06426530B1 High performance direct coupled FET memory cell 失效
标题翻译：高性能直接耦合FET存储单元
公开(公告)号：US06426530B1
公开(公告)日：2002-07-30
申请号：US09568663
申请日：2000-05-10
申请人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
发明人： Claude L. Bertin , John E. Cronin , Erik L. Hedberg , Jack A. Mandelman
IPC分类号： H01L2976
CPC分类号： H01L27/11 , Y10S257/903
摘要： A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETs, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer. Second, the cell pass gates are formed on a pass gate or Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the preferred latch layer.
摘要翻译：一对直接耦合的场效应晶体管（FET），直接耦合的FET的锁存器，包括直接耦合的FET的锁存器的静态随机存取存储器（SRAM）单元和形成直接耦合的FET结构的过程，锁存器和SRAM单元。可以是PFET，NFET或者其中之一的垂直FET是由栅极氧化物SiO 2分离的外延生长的NPN或PNP堆叠。每个设备的门是该对的另一个设备的源或漏极。优选实施例锁存器包括两对这样的直接耦合的垂直FET对，连接在一起以形成交叉耦合的反相器。通路栅极层结合到优选实施例锁存器的一个表面上以形成优选实施例SRAM单元的阵列。 SRAM单元可以包括一个或两个传递门。优选实施例SRAM过程具有三个主要步骤。首先，优选实施例的锁存器形成在硅晶片上的氧化物层中。第二，在传输门或输入/输出（I / O）层上形成单元传输门。第三，I / O层被粘合并连接到优选的锁存层。

3. 发明授权

US06255899B1 Method and apparatus for increasing interchip communications rates 失效
标题翻译：提高芯片间通信速率的方法和装置
公开(公告)号：US06255899B1
公开(公告)日：2001-07-03
申请号：US09388164
申请日：1999-09-01
申请人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01L2500
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06517 , H01L2225/0652 , H01L2225/06555 , H01L2225/06589 , H01L2924/00014 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15192 , H01L2924/16152 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： An assembly is provided that includes an interposer having first and second substantially flat, opposed surfaces, and at least one speed critical signal line extending directly through the interposer from the first surface to the second surface. A first IC is coupled to the first surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. A second IC is coupled to the second surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. Preferably at least one non-speed critical signal line is provided within the interposer and is coupled to a second external connection mechanism of the first IC and/or the second IC for delivering non-speed critical signals thereto or for receiving such signals therefrom. A chip carrier having a cavity formed therein also may be provided wherein the second surface of the interposer is coupled to the chip carrier and the second IC is disposed within the cavity. One or more carrier signal lines may be provided within the chip carrier and coupled between the interposer and the second IC. The first and/or the second IC also may comprise control logic adapted to select a number of drivers within either IC that drive a particular signal line.
摘要翻译：提供了一种组件，其包括具有第一和第二基本上平坦的相对表面的插入件以及至少一个直线从第一表面延伸到第二表面的速度临界信号线。第一IC耦合到插入器的第一表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。第二IC耦合到插入器的第二表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。优选地，在插入器内提供至少一个非速度临界信号线，并且耦合到第一IC和/或第二IC的第二外部连接机构，用于向其递送非速度关键信号或用于从其接收这样的信号。还可以提供其中形成有空腔的芯片载体，其中插入器的第二表面耦合到芯片载体，并且第二IC设置在空腔内。可以在芯片载体内提供一个或多个载波信号线，并且耦合在插入器和第二IC之间。第一和/或第二IC还可以包括适于选择驱动特定信号线的IC内的多个驱动器的控制逻辑。

4. 发明授权

US06518112B2 High performance, low power vertical integrated CMOS devices 失效
公开(公告)号：US06518112B2
公开(公告)日：2003-02-11
申请号：US09899262
申请日：2001-07-06
申请人： Michael D. Armacost , Claude L. Bertin , Erik L. Hedberg , Jack A. Mandelman
发明人： Michael D. Armacost , Claude L. Bertin , Erik L. Hedberg , Jack A. Mandelman
IPC分类号： H01L31119
CPC分类号： H01L27/11 , H01L21/823885 , H01L21/84 , H01L27/1104 , H01L27/1203 , Y10S257/903
摘要： A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETs; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer. The SRAM cell may be radiation hardened by selectively thickening gate layers to increase storage node capacitance, providing high resistance cell wiring or by including a multi-layered gate oxide layer of NO or ONO, or by any combination thereof.

5. 发明授权

US06297531B2 High performance, low power vertical integrated CMOS devices 失效
标题翻译：高性能，低功耗的垂直集成CMOS器件
公开(公告)号：US06297531B2
公开(公告)日：2001-10-02
申请号：US09002399
申请日：1998-01-05
申请人： Michael D. Armacost , Claude L. Bertin , Erik L. Hedberg , Jack A. Mandelman
发明人： Michael D. Armacost , Claude L. Bertin , Erik L. Hedberg , Jack A. Mandelman
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L21/823885 , H01L21/84 , H01L27/1104 , H01L27/1203 , Y10S257/903
摘要： A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETS; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer. The SRAM cell may be radiation hardened by selectively thickening gate layers to increase storage node capacitance, providing high resistance cell wiring or by including a multi-layered gate oxide layer of NO or ONO, or by any combination thereof.
摘要翻译：可以是N型FET（NFET）或P型FET（PFET）的垂直场效应晶体管（FET）; 可以是两个或更多个NFET或两个或更多个PFETS的多器件垂直结构; 逻辑门包括至少一个垂直FET或至少一个多器件垂直; 包括至少一个垂直FET的静态随机存取存储器（SRAM）单元和阵列; 包括至少一个这样的SRAM单元的存储器阵列; 以及形成垂直FET结构的过程，垂直多器件（multi-FET）结构，逻辑门和SRAM单元。垂直FET是NPN或PNP的外延生长层叠堆叠，其中多晶硅栅极层的侧面与器件的沟道层相邻。多FET结构可以通过形成与相同沟道层相邻的两个或多个栅极的侧面，或者通过在相同的堆叠中形成多个通道层，例如PNPNP或NPNPN，每个具有其自己的栅极，即侧面的多晶硅栅极层。 SRAM单元可以通过选择性地增厚栅极层而辐射硬化，以增加存储节点电容，提供高电阻电池布线或者通过包括NO或ONO的多层栅极氧化物层或其任何组合。

6. 发明授权

US06396120B1 Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application 失效
标题翻译：硅抗熔丝结构，绝缘体上的体和硅绝缘体制造方法和应用
公开(公告)号：US06396120B1
公开(公告)日：2002-05-28
申请号：US09527191
申请日：2000-03-17
申请人： Claude L Bertin , Toshiharu Furukawa , Erik L. Hedberg , Jack A. Mandelman , William R. Tonti , Richard Q. Williams
发明人： Claude L Bertin , Toshiharu Furukawa , Erik L. Hedberg , Jack A. Mandelman , William R. Tonti , Richard Q. Williams
IPC分类号： H01L2972
CPC分类号： H01L29/78696 , H01L21/823412 , H01L21/823456 , H01L23/5252 , H01L27/10897 , H01L27/1203 , H01L29/42384 , H01L2924/0002 , H01L2924/00
摘要： A method and semiconductor structure that uses a field enhanced region where the oxide thickness is substantially reduced, thereby allowing antifuse programming at burn-in voltages which do not damage the standard CMOS logic. The semiconductor device comprises a substrate that has a raised protrusion terminating at a substantially sharp point, an insulator layer over the raised protrusion sufficiently thin to be breached by a breakdown voltage applied to the sharp point, a region comprised of a material on the insulator over the raised protrusion for becoming electrically coupled to the substrate after the insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to the substrate. In a second embodiment, the semiconductor device comprises a substrate having a trough formed in a top surface of the substrate, a relatively thick insulator layer over the top surface of the substrate, a relatively thin insulator layer over the trough that is breached by a breakdown voltage applied to the trough, a region comprised of a material on the relatively thin insulator layer over the trough for becoming electrically coupled to the substrate after the relatively thin insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to said substrate.
摘要翻译：一种使用场强增强区域的方法和半导体结构，其中氧化物厚度大大降低，从而允许在不损坏标准CMOS逻辑的老化电压下进行反熔丝编程。半导体器件包括具有突出的突起终止于基本尖锐点的衬底，凸起突起上的绝缘体层足够薄以致被施加到尖锐点的击穿电压所破坏，由绝缘体上的材料构成的区域在绝缘体层被击穿电压破坏之后用于电耦合到衬底的凸起突起，以及用于向衬底提供击穿电压的触点。在第二实施例中，半导体器件包括在衬底的顶表面中形成有槽的衬底，在衬底的顶表面上方的相对较厚的绝缘体层，在槽的相对较薄的绝缘体层，其被破坏电压施加到槽，由比较薄的绝缘体层上的材料组成的区域，该沟槽在相对较薄的绝缘体层被击穿电压破坏之后用于变成与电极耦合的衬底;以及用于将击穿电压提供给所述基板。

7. 发明授权

US06574763B1 Method and apparatus for semiconductor integrated circuit testing and burn-in 失效
标题翻译：用于半导体集成电路测试和老化的方法和装置
公开(公告)号：US06574763B1
公开(公告)日：2003-06-03
申请号：US09473886
申请日：1999-12-28
申请人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
发明人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
IPC分类号： G01R3128
CPC分类号： G01R31/287
摘要： A burn-in process is provided for a memory array having redundant bits and addressable storage locations. The burn-in process includes the steps of raising the temperature of the memory array to a pre-determined temperature, testing all bits in the array, detecting faulty bits and operable bits, replacing faulty bits with redundant operable bits, correcting any defects in the array in-situ, and lowering the temperature of the memory array to ambient temperature to complete the burn-in process. An apparatus for carrying out the above process is provided that includes a test circuit for generating a test pattern and for applying the test pattern to the memory array so as to test all bits within the memory array. A comparison circuit, coupled to the test circuit and adapted to couple to the memory array, compares an actual response and an expected response of the memory array to the test pattern and detects faulty and operable bits based thereon. A failed address buffer register, coupled to the comparison circuit and to the test circuit, stores an address of each addressable storage location that has a faulty bit. Sparing control logic, coupled to the failed address buffer register and adapted to couple to the memory array, reads out each address stored by the failed address buffer register and replaces each faulty bit with a redundant operable bit.
摘要翻译：为具有冗余位和可寻址存储位置的存储器阵列提供老化过程。老化过程包括以下步骤：将存储器阵列的温度升高到预定温度，测试阵列中的所有位，检测故障位和可操作位，用冗余的可操作位代替故障位，校正在阵列原位，并将存储器阵列的温度降低到环境温度以完成老化过程。提供了一种用于执行上述处理的装置，其包括用于生成测试图案并将测试图案应用于存储器阵列的测试电路，以便测试存储器阵列内的所有位。耦合到测试电路并且适于耦合到存储器阵列的比较电路将存储器阵列的实际响应和预期响应与测试模式进行比较，并基于此检测故障和可操作的位。耦合到比较电路和测试电路的故障地址缓冲寄存器存储具有错误位的每个可寻址存储位置的地址。冗余控制逻辑耦合到故障地址缓冲寄存器并适于耦合到存储器阵列，读出由故障地址缓冲寄存器存储的每个地址，并用冗余可操作位替换每个故障位。

8. 发明授权

US5561622A Integrated memory cube structure 失效
标题翻译：集成内存立方体结构
公开(公告)号：US5561622A
公开(公告)日：1996-10-01
申请号：US120993
申请日：1993-09-13
申请人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
发明人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
IPC分类号： G11C5/00 , H01L25/065 , G11C5/06 , H01L23/02
CPC分类号： H01L25/0657 , G11C5/06 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/10253
摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译：一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

9. 发明授权

US06420925B1 Programmable latch device with integrated programmable element 有权
标题翻译：具有集成可编程元件的可编程锁存器件
公开(公告)号：US06420925B1
公开(公告)日：2002-07-16
申请号：US09757267
申请日：2001-01-09
申请人： John A. Fifield , Erik L. Hedberg , Claude L. Bertin , Nicholas M. van Heel
发明人： John A. Fifield , Erik L. Hedberg , Claude L. Bertin , Nicholas M. van Heel
IPC分类号： H01H3776
CPC分类号： H03K3/356008 , G11C17/18
摘要： According to the present invention, a programable latch device for use in personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment programmable latch device can use both fuses and antifuses as programmable elements. The programmable latch device provides a solid digital output indicative of the state of the programmable device, and can be reliably read to provide customization and personalization of associated semiconductor devices. The preferred embodiment programable latch device includes an integrated fuse or antifuse as a programmable element in the latch device. By integrating the programmable element into the latch, device size and complexity is minimized. In particular, the number of transistors required drops considerably when compared to prior art approaches.
摘要翻译：根据本发明，提供了用于个性化半导体器件的可编程锁存器件，其克服了现有技术的限制。优选实施例可编程锁存器件可以使用熔丝和反熔丝作为可编程元件。可编程锁存器件提供指示可编程器件状态的实心数字输出，并且可被可靠地读取以提供相关半导体器件的定制和个性化。优选实施例可编程锁存装置包括作为锁存装置中的可编程元件的集成熔丝或反熔丝。通过将可编程元件集成到锁存器中，器件尺寸和复杂度最小化。特别地，与现有技术方法相比，所需的晶体管的数量显着下降。

10. 发明授权

US06233184B1 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06233184B1
公开(公告)日：2001-05-15
申请号：US09191954
申请日：1998-11-13
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

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