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11. 发明授权

US07132350B2 Method for manufacturing a programmable eraseless memory 有权
标题翻译：制造可编程擦除存储器的方法
公开(公告)号：US07132350B2
公开(公告)日：2006-11-07
申请号：US10641897
申请日：2003-08-15
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Jer Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L21/479 , H01L21/326
CPC分类号： G11C11/5692 , H01L27/101
摘要： A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：一种用于制造电可编程非易失性存储单元的方法包括在衬底上形成第一电极，在第一电极上形成具有特征在于应力的响应逐渐变化的特性的材料的电极间层，并形成第二电极在材料的电极间层之上。电极间层包括在第一和第二电极之间的介电层，例如超薄氧化物。可编程电阻或其他属性通过强调介电层来表示存储的数据来建立。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

12. 发明授权

US07057938B2 Nonvolatile memory cell and operating method 有权
标题翻译：非易失性存储单元和操作方法
公开(公告)号：US07057938B2
公开(公告)日：2006-06-06
申请号：US10756777
申请日：2004-01-14
申请人： Chih Chieh Yeh , Hung Yueh Chen , Yi Ying Liao , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Hung Yueh Chen , Yi Ying Liao , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C16/0475 , H01L21/28282 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： One embodiment of the present invention provides a system having a nonvolatile memory comprising a p type semiconductor substrate, an oxide layer over the p type semiconductor substrate, a nitride layer over the oxide layer, an additional oxide layer over the nitride layer, a gate over the additional oxide layer, two N+ junctions in the p type semiconductor layer, a source and drain respectively formed in the two N+ junctions, a first bit and a second bit in the nonvolatile memory, and accordingly at least two states of operation (i.e., erase and program) therefor. That is, one bit in the nonvolatile memory can either be in an erase state or program state. For erasing a bit, electrons are injected at the gate of the nonvolatile memory. For programming a bit, electric holes are injected or electrons are reduced for that bit. The present invention also provides a method for sensing and reading at least one bit in a nonvolatile memory comprising applying a bias voltage to the memory, detecting a threshold voltage or read current, comparing the threshold voltage with a reference voltage or comparing the read current with a reference current, and identifying the at least one bit as erased or programmed.
摘要翻译：本发明的一个实施例提供一种具有非易失性存储器的系统，其包括ap型半导体衬底，p型半导体衬底上的氧化物层，氧化物层上方的氮化物层，氮化物层上的附加氧化物层，分别形成在两个N +结中的源极和漏极，非易失性存储器中的第一位和第二位，以及相应地至少两个操作状态（即擦除）的附加氧化物层，p型半导体层中的两个N +结，和程序）。也就是说，非易失性存储器中的一位可以处于擦除状态或程序状态。为了擦除一点，电子注入非易失性存储器的栅极。为了编程一点，注入电孔或减少电子的位。本发明还提供了一种用于感测和读取非易失性存储器中的至少一个位的方法，包括向存储器施加偏置电压，检测阈值电压或读取电流，将阈值电压与参考电压进行比较，或将读取的电流与参考电流，并将所述至少一个位识别为擦除或编程。

13. 发明授权

US07397701B2 Method and apparatus for operating a string of charge trapping memory cells 有权
标题翻译：用于操作电荷俘获存储器单元串的方法和装置
公开(公告)号：US07397701B2
公开(公告)日：2008-07-08
申请号：US11279720
申请日：2006-04-13
申请人： Chih Chieh Yeh , Wen Jer Tsai , Yi Ying Liao
发明人： Chih Chieh Yeh , Wen Jer Tsai , Yi Ying Liao
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/10 , G11C16/3445 , G11C16/3459
摘要： An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage state.
摘要翻译：电荷捕获非易失性存储单元的阵列被布置在几列单元格中，每列单元排列成一串，例如NAND串。每个单元格不存储单个电荷存储状态。

14. 发明申请

US20070087523A1 Recessed shallow trench isolation 有权
标题翻译：凹槽浅沟隔离
公开(公告)号：US20070087523A1
公开(公告)日：2007-04-19
申请号：US11249228
申请日：2005-10-13
申请人： Chih Chieh Yeh , Wen Jer Tsai
发明人： Chih Chieh Yeh , Wen Jer Tsai
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573
摘要： In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations. In some embodiments, recessed shallow trench isolation structures are formed.
摘要翻译：在一些实施例中，存储器集成电路在存储器集成电路的存储器电路和存储器集成电路的控制电路中具有不同的浅沟槽隔离结构。隔离电介质以不同的程度填充浅沟槽隔离结构的沟槽。在一些实施例中，存储器集成电路具有具有浅沟槽隔离结构和中间区域的存储器电路。存储器电路支持在支持具有不同取向的多个电流分量的相邻非易失性存储器件之间的通道。在一些实施例中，形成凹陷的浅沟槽隔离结构。

15. 发明申请

US20090155978A1 Recessed Shallow Trench Isolation 有权
标题翻译：嵌入式浅沟槽隔离
公开(公告)号：US20090155978A1
公开(公告)日：2009-06-18
申请号：US12392454
申请日：2009-02-25
申请人： Chih Chieh Yeh , Wen Jer Tsai
发明人： Chih Chieh Yeh , Wen Jer Tsai
IPC分类号： H01L21/762 , H01L21/8246
CPC分类号： H01L21/76229 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573
摘要： In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees.In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations.In some embodiments, recessed shallow trench isolation structures are formed.
摘要翻译：在一些实施例中，存储器集成电路在存储器集成电路的存储器电路和存储器集成电路的控制电路中具有不同的浅沟槽隔离结构。隔离电介质以不同的程度填充浅沟槽隔离结构的沟槽。在一些实施例中，存储器集成电路具有具有浅沟槽隔离结构和中间区域的存储器电路。存储器电路支持在支持具有不同取向的多个电流分量的相邻非易失性存储器件之间的通道。在一些实施例中，形成凹陷的浅沟槽隔离结构。

16. 发明授权

US07321145B2 Method and apparatus for operating nonvolatile memory cells with modified band structure 有权
标题翻译：用于操作具有改进的带结构的非易失性存储单元的方法和装置
公开(公告)号：US07321145B2
公开(公告)日：2008-01-22
申请号：US11249832
申请日：2005-10-13
申请人： Chih Chieh Yeh , Wen Jer Tsai
发明人： Chih Chieh Yeh , Wen Jer Tsai
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/28282 , B82Y10/00 , G11C16/10 , H01L29/1054 , H01L29/42328 , H01L29/42332 , H01L29/7843 , H01L29/7881 , H01L29/7923
摘要： A nonvolatile memory cell with a charge storage structure is read by measuring current (such as band-to-band current) between the substrate region of the memory cell and at least one of the current carrying nodes of the memory cell. To enhance the operation of the nonvolatile memory cell, the band structure engineering is used to alter the band structure between a bulk part of the device and another part of the device supporting the measurement current.
摘要翻译：具有电荷存储结构的非易失性存储单元通过测量存储单元的衬底区域与存储单元的至少一个载流节点之间的电流（例如带间电流）来读取。为了增强非易失性存储单元的操作，使用带结构工程来改变装置的主体部分和支持测量电流的装置的另一部分之间的带结构。

17. 发明授权

US07133317B2 Method and apparatus for programming nonvolatile memory 有权
标题翻译：用于非易失性存储器编程的方法和装置
公开(公告)号：US07133317B2
公开(公告)日：2006-11-07
申请号：US11064316
申请日：2005-02-23
申请人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai
发明人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0475 , G11C16/0491
摘要： Programming nonvolatile memory cells is affected by the program disturb effect which causes data accuracy issues with nonvolatile memory. Rather than masking the voltage conditions that cause the program disturb effect, voltages are applied to neighboring nonvolatile memory cells, which takes advantage of the program disturb effect to program multiple cells quickly.
摘要翻译：编程非易失性存储单元受程序干扰影响，导致非易失性存储器的数据精度问题。不是屏蔽导致程序干扰效应的电压条件，而是将电压施加到相邻的非易失性存储单元，利用程序干扰效应来快速编程多个单元。

18. 发明授权

US07514742B2 Recessed shallow trench isolation 有权
标题翻译：凹槽浅沟隔离
公开(公告)号：US07514742B2
公开(公告)日：2009-04-07
申请号：US11249228
申请日：2005-10-13
申请人： Chih Chieh Yeh , Wen Jer Tsai
发明人： Chih Chieh Yeh , Wen Jer Tsai
IPC分类号： H01L27/108
CPC分类号： H01L21/76229 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573
摘要： In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees.In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations.In some embodiments, recessed shallow trench isolation structures are formed.
摘要翻译：在一些实施例中，存储器集成电路在存储器集成电路的存储器电路和存储器集成电路的控制电路中具有不同的浅沟槽隔离结构。隔离电介质以不同的程度填充浅沟槽隔离结构的沟槽。在一些实施例中，存储器集成电路具有具有浅沟槽隔离结构和中间区域的存储器电路。存储器电路支持在支持具有不同取向的多个电流分量的相邻非易失性存储器件之间的通道。在一些实施例中，形成凹陷的浅沟槽隔离结构。

19. 发明申请

US20090080254A1 Gated Diode Nonvolatile Memory Cell Array 有权
标题翻译：门极二极管非易失性存储单元阵列
公开(公告)号：US20090080254A1
公开(公告)日：2009-03-26
申请号：US12326706
申请日：2008-12-02
申请人： Yi Ying Liao , Wen Jer Tsai , Chih Chieh Yeh
发明人： Yi Ying Liao , Wen Jer Tsai , Chih Chieh Yeh
IPC分类号： G11C16/02 , G11C11/36
CPC分类号： G11C11/36 , B82Y10/00 , G11C16/02 , G11C2216/06 , H01L27/1021 , H01L29/8616
摘要： A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated.
摘要翻译：存储器集成电路具有垂直分层的存储器阵列。这些存储器阵列包括字线和位线。字线和位线之间的交点包括二极管和存储器状态存储元件。二极管和存储器存储元件连接在字线和位线之间。交叉处的二极管包括第一二极管节点和第二二极管节点。存储器集成电路的各个方面以各种方式电互连，例如相应的字线，对应的第一二极管节点或不同存储器阵列的相应的第二二极管节点电互连。存储器集成电路的各个方面以各种方式隔离，例如隔离不同存储器阵列的字线，第一二极管节点或第二二极管节点。

20. 发明授权

US07272043B2 Operation methods for a non-volatile memory cell in an array 有权
标题翻译：阵列中非易失性存储单元的操作方法
公开(公告)号：US07272043B2
公开(公告)日：2007-09-18
申请号：US11020269
申请日：2004-12-27
申请人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai
发明人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/0483
摘要： A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.
摘要翻译：一种通过在选定字线的不同侧面施加不同的Vpass电压来减少电荷俘获层存储单元中的门扰动的方法。较高的Vpass电压用于传递较高的源极/漏极电压，较低的Vpass电压用于通过较低的源极/漏极电压。通过控制所选字线的不同侧的Vpass电压，可以减小施加Vpass电压时在栅极区域中建立的垂直场。减小的垂直场导致抑制的门扰动。该方法还包括新颖的位线偏置方案，其可以进一步减小垂直场，从而可进一步抑制门扰动，特别是在存储器单元阵列中。

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