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11. 发明授权

US07315082B2 Semiconductor device having integrated circuit contact 失效
标题翻译：具有集成电路接触的半导体器件
公开(公告)号：US07315082B2
公开(公告)日：2008-01-01
申请号：US10443471
申请日：2003-05-22
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L23/48
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
摘要翻译：公开了一种用于在集成电路的制造中形成垂直触点的工艺以及如此制造的器件。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

12. 发明授权

US07064036B2 Dual-gate transistor device and method of forming a dual-gate transistor device 有权
标题翻译：双栅极晶体管器件和形成双栅极晶体管器件的方法
公开(公告)号：US07064036B2
公开(公告)日：2006-06-20
申请号：US10932192
申请日：2004-09-01
申请人： John K. Zahurak , Brent Keeth , Charles H. Dennison
发明人： John K. Zahurak , Brent Keeth , Charles H. Dennison
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/76897 , H01L21/76898 , H01L21/84 , H01L27/1203 , H01L29/78621 , H01L29/78645 , H01L29/78648
摘要： Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.
摘要翻译：根据本发明的实施例提供了形成双门限半导体绝缘体（SOI）器件的方法。这样的方法包括形成与SOI衬底的半导体层的第一侧可操作地相邻的第一晶体管结构。绝缘体层材料从第一晶体管结构的源极/漏极接触结构和第二晶体管结构之间的半导体层的第二侧被去除，第二晶体管结构可操作地邻近半导体层的第二侧并与第一晶体管结构对准。

13. 发明授权

US06919578B2 Utilizing atomic layer deposition for programmable device 失效
公开(公告)号：US06919578B2
公开(公告)日：2005-07-19
申请号：US10313785
申请日：2002-12-06
申请人： Tyler A. Lowrey , Charles H. Dennison
发明人： Tyler A. Lowrey , Charles H. Dennison
IPC分类号： H01L21/285 , H01L21/768 , H01L27/24 , H01L47/00
CPC分类号： H01L21/7685 , H01L21/28562 , H01L21/76888 , H01L27/24
摘要： In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.

14. 发明授权

US06818496B2 Silicon on insulator DRAM process utilizing both fully and partially depleted devices 有权
标题翻译：使用完全和部分耗尽的器件的绝缘体上硅DRAM工艺
公开(公告)号：US06818496B2
公开(公告)日：2004-11-16
申请号：US10265426
申请日：2002-10-07
申请人： Charles H. Dennison , John K. Zahurak
发明人： Charles H. Dennison , John K. Zahurak
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/3081 , H01L21/31111 , H01L21/31116 , H01L21/84 , H01L27/10811 , H01L27/10873 , H01L27/1203
摘要： This invention relates to the field of semiconductor integrated circuits and, particularly to stand-alone and embedded memory chips fabricated on Silicon-on-Insulator (SOI) substrates and devices. Partially depleted (PD) and fully depleted (FD) devices are utilized on the same chip. The invention is a process flow utilizing fully depleted SOI devices in one area of the chip and partially depleted SOI devices in selected other areas of the chip. The choice of fully depleted or partially depleted is solely determined by the circuit application in that specific area of the chip. The invention is able to be utilized in accordance with DRAM processing, and especially embedded DRAMs with their large proportion of associated logic circuitry.
摘要翻译：本发明涉及半导体集成电路领域，特别涉及制造在绝缘体上硅（SOI）衬底和器件上的独立和嵌入式存储器芯片。部分耗尽（PD）和完全耗尽（FD）器件在同一芯片上被利用。本发明是在芯片的一个区域中利用完全耗尽的SOI器件和在芯片的选定其他区域中部分耗尽的SOI器件的工艺流程。完全耗尽或部分耗尽的选择仅由芯片的该特定区域中的电路应用决定。本发明能够根据DRAM处理，特别是具有大比例的相关逻辑电路的嵌入式DRAM。

15. 发明授权

US06759285B2 Methods of forming transistors 失效
公开(公告)号：US06759285B2
公开(公告)日：2004-07-06
申请号：US10071031
申请日：2002-02-07
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L2100
CPC分类号： H01L29/6675 , H01L27/11 , H01L27/1108 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78648 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

16. 发明授权

US06710420B2 Semiconductor construction of a trench 有权
标题翻译：半导体构造的沟槽
公开(公告)号：US06710420B2
公开(公告)日：2004-03-23
申请号：US10241923
申请日：2002-09-11
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

17. 再颁专利

USRE38049E1 Optimized container stacked capacitor dram cell utilizing sacrificial oxide deposition and chemical mechanical polishing 失效
标题翻译：利用牺牲氧化物沉积和化学机械抛光优化容器堆叠电容器电容器
公开(公告)号：USRE38049E1
公开(公告)日：2003-03-25
申请号：US08759058
申请日：1996-10-07
申请人： Charles H. Dennison , Michael A. Walker
发明人： Charles H. Dennison , Michael A. Walker
IPC分类号： H01L2120
CPC分类号： H01L28/91
摘要： An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the container capacitor by etching an opening (or contact opening) into a low etch rate oxide. The contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls. Within the thin poly lining of the oxide container a high etch-rate oxide, such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container. The high etch-rate oxide is planarized back to the thin poly and the resulting exposed poly is then removed to separate neighboring containers. The two oxides, having different etch rates, are then etched thereby leaving a free-standing poly container cell with 100% (or all) of the higher etch rate oxide removed and a pre-determined oxide surrounding the container still intact.
摘要翻译：修改现有的堆叠电容器制造工艺以构建三维堆叠容器电容器。本发明通过将开口（或接触开口）蚀刻成低蚀刻速率氧化物来开发容器电容器。接触开口用作与开口壁的侧面一致的沉积多晶硅的形式。在氧化物容器的薄多孔衬里内，在整个结构上沉积诸如臭氧TEOS的高蚀刻速率氧化物，从而桥接穿过氧化物容器的顶部。将高蚀刻速率的氧化物平面化回到薄的多晶硅上，然后除去所得到的暴露的聚合物以分离相邻的容器。然后蚀刻具有不同蚀刻速率的两种氧化物，从而留下独立的多容器电池，其具有100％（或全部）更高蚀刻速率的氧化物，并且包围容器的预定氧化物仍然完整。

18. 发明授权

US06511867B2 Utilizing atomic layer deposition for programmable device 有权
标题翻译：利用原子层沉积可编程器件
公开(公告)号：US06511867B2
公开(公告)日：2003-01-28
申请号：US09896529
申请日：2001-06-30
申请人： Tyler A. Lowrey , Charles H. Dennison
发明人： Tyler A. Lowrey , Charles H. Dennison
IPC分类号： H01L2182
CPC分类号： H01L21/7685 , H01L21/28562 , H01L21/76888 , H01L27/24
摘要： In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.
摘要翻译：在一方面，提供一种设置和重新编程可编程设备的状态的设备。在一方面，提供了一种方法，使得通过暴露接触的电介质形成开口，接触形成在基底上。利用原子层沉积（ALD）将电极保形地沉积在电介质的壁上。可编程材料形成在电极上，导体形成可编程材料。在一个方面，在电极和可编程材料之间利用ALD共形沉积屏障。

19. 发明授权

US06482707B1 Method of improving static refresh 有权
标题翻译：改善静态刷新的方法
公开(公告)号：US06482707B1
公开(公告)日：2002-11-19
申请号：US09532094
申请日：2000-03-21
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L29/6656
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
摘要翻译：公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。第一次毯式离子注入工艺具有第一能级和剂量。该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。第二次毯子离子注入过程具有第二能量水平和剂量。所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

20. 发明授权

US06479332B2 Methods of forming integrated circuitry 有权
标题翻译：形成集成电路的方法
公开(公告)号：US06479332B2
公开(公告)日：2002-11-12
申请号：US09884293
申请日：2001-06-18
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L2100
CPC分类号： H01L29/6675 , H01L27/11 , H01L27/1108 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78648 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
摘要翻译：电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。这样可用于制造薄膜晶体管和其他电路。

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