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1. 发明授权

US06689649B2 Methods of forming transistors 失效
标题翻译：形成晶体管的方法
公开(公告)号：US06689649B2
公开(公告)日：2004-02-10
申请号：US09884292
申请日：2001-06-18
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L2100
CPC分类号： H01L29/6675 , H01L27/11 , H01L27/1108 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78648 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
摘要翻译：电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。这样可用于制造薄膜晶体管和其他电路。

2. 发明授权

US06306696B1 Methods of forming integrated circuitry methods of forming thin film transistors, integrated circuitry and thin film transistors 失效
标题翻译：形成薄膜晶体管，集成电路和薄膜晶体管的集成电路方法的方法
公开(公告)号：US06306696B1
公开(公告)日：2001-10-23
申请号：US09025214
申请日：1998-02-18
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L2100
CPC分类号： H01L29/6675 , H01L27/11 , H01L27/1108 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78648 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically a etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
摘要翻译：电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性地蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。这样可用于制造薄膜晶体管和其他电路。

3. 发明授权

US5650655A Integrated circuitry having electrical interconnects 失效
标题翻译：具有电互连的集成电路
公开(公告)号：US5650655A
公开(公告)日：1997-07-22
申请号：US561105
申请日：1995-11-21
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6675 , H01L27/11 , H01L27/1108 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78648 , H01L2924/0002 , Y10S257/903
摘要： The disclosure pertains to a bottom and top gated thin film transistor and other circuitry constructions. In the thin film transistor construction, the top gate electrode (preferably polysilicon) overlaps with the channel region, and the top gate electrode has an electrically conductive sidewall (preferably oxide). The bottom gate electrode (preferably polysilicon) has an outer surface area which includes a portion which extends outwardly beyond the top gate electrode sidewall. An electrically conductive sidewall link overlies the electrically insulated channel region sidewall and extends between the top gate sidewall and bottom gate outer surface portion to electrically interconnect the top and bottom gate electrodes. The insulated channel region sidewall is insulated by an insulating sidewall spacer. The insulating sidewall spacer partially overlaps the top gate electrode electrically conductive sidewall. More generally beyond thin film transistor constructions, two conductive layers are provided which are separated by an insulating material on a semiconductor wafer. Each has an outer sidewall. An electrically conductive sidewall link is positioned over and electrically interconnects the respective outer sidewalls of the two conductive layers. Further, a mid conductive layer is provided which is electrically isolated from and positioned between the inner and outer conductive layers. This layer has a sidewall also covered by an insulating material. The insulating material partially overlaps the outer conductive layer sidewall. The electrically conductive sidewall link is positioned over the insulating material.
摘要翻译：本公开涉及底部和顶部门控薄膜晶体管以及其它电路结构。在薄膜晶体管结构中，顶栅电极（优选多晶硅）与沟道区重叠，顶栅电极具有导电侧壁（优选氧化物）。底栅电极（优选多晶硅）具有包括向外延伸超过顶栅电极侧壁的部分的外表面区域。导电侧壁连接部覆盖在电绝缘沟道区域侧壁上，并在顶部栅极侧壁和底部栅极外表面部分之间延伸，以电连接顶部和底部栅电极。绝缘通道区域侧壁由绝缘侧壁隔离物绝缘。绝缘侧壁间隔件部分地与顶部栅电极导电侧壁重叠。更一般地，超过薄膜晶体管结构，提供了两个导电层，其由半导体晶片上的绝缘材料分隔开。每个都有一个外侧壁。导电侧壁连接件位于两个导电层的相应的外侧壁之间并电连接。此外，提供了中间导电层，其与内导电层和外导电层电隔离并定位在其间。该层具有也被绝缘材料覆盖的侧壁。绝缘材料部分地与外导电层侧壁重叠。导电侧壁连接件位于绝缘材料上方。

4. 发明授权

US5616934A Fully planarized thin film transistor (TFT) and process to fabricate same 失效
标题翻译：全平面化薄膜晶体管（TFT）及其制造方法
公开(公告)号：US5616934A
公开(公告)日：1997-04-01
申请号：US621766
申请日：1996-03-22
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L29/68 , H01L21/265
CPC分类号： H01L29/66757 , H01L27/11 , H01L27/1108 , H01L29/6675 , H01L29/78618 , Y10S257/903 , Y10S438/964
摘要： The invention is directed to a thin film transistor (TFT) fabricated by using a planarized poly plug as the bottom gate for use in any integrated circuit and in particular an static random access memory (SRAM). The TFT is used in an SRAM device to form a planarized SRAM cell comprising: a pulldown transistor having a control gate and source/drain terminals; a planarized insulating layer having grooves therein, each groove providing access to an underlying conductive material; a planarized conductive plug residing inside each groove, whereby a first conductive plug forms a thin film transistor gate connecting to an to an adjacent inverter and a second conductive plug provides connection to the gate of the pulldown device; a gate dielectric overlying the first planarized conductive plug; and a patterned semiconductive layer doped such that a channel region aligns to each thin film transistor gate and a source/drain region aligns to each side of the channel region is formed.
摘要翻译：本发明涉及通过使用平面化多晶硅塞作为用于任何集成电路，特别是静态随机存取存储器（SRAM）的底栅制造的薄膜晶体管（TFT）。 TFT用于SRAM器件以形成平坦化SRAM单元，包括：具有控制栅极和源极/漏极端子的下拉晶体管; 平坦化绝缘层，其中具有凹槽，每个凹槽提供对下面的导电材料的接触; 位于每个凹槽内的平坦化导电插头，由此第一导电插塞形成连接到相邻逆变器的薄膜晶体管栅极，第二导电插头提供到下拉器件的栅极的连接; 覆盖所述第一平坦化导电插塞的栅极电介质; 以及被掺杂的图案化半导体层，使得沟道区域对齐于每个薄膜晶体管栅极，并且形成与沟道区域的每一侧对准的源极/漏极区域。

5. 发明授权

US5434103A Method of forming an electrical connection 失效
标题翻译：形成电气连接的方法
公开(公告)号：US5434103A
公开(公告)日：1995-07-18
申请号：US235564
申请日：1994-04-28
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L21/441
CPC分类号： H01L29/6675 , H01L27/11 , H01L27/1108 , H01L29/78624 , Y10S257/90
摘要： An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
摘要翻译：电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。这样可用于制造薄膜晶体管和其他电路。

6. 发明授权

US06759285B2 Methods of forming transistors 失效
公开(公告)号：US06759285B2
公开(公告)日：2004-07-06
申请号：US10071031
申请日：2002-02-07
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L2100
CPC分类号： H01L29/6675 , H01L27/11 , H01L27/1108 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78648 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

7. 发明授权

US06479332B2 Methods of forming integrated circuitry 有权
标题翻译：形成集成电路的方法
公开(公告)号：US06479332B2
公开(公告)日：2002-11-12
申请号：US09884293
申请日：2001-06-18
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L2100
CPC分类号： H01L29/6675 , H01L27/11 , H01L27/1108 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78648 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
摘要翻译：电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。这样可用于制造薄膜晶体管和其他电路。

8. 发明授权

US06251714B1 Method of making thin film field effect transistors 失效
标题翻译：制造薄膜场效应晶体管的方法
公开(公告)号：US06251714B1
公开(公告)日：2001-06-26
申请号：US08989366
申请日：1997-12-12
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L2184
CPC分类号： H01L29/66757 , H01L27/11 , H01L27/1108 , H01L29/6675 , H01L29/66765 , H01L29/78618 , H01L29/78678
摘要： A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.
摘要翻译：薄膜场效应晶体管包括：a）薄膜沟道区; b）与薄膜通道区相邻的一对相对的导电的第一和第二源/漏区; c）栅极绝缘体和位于薄膜通道区域附近的栅极，用于对沟道区域进行电激励以导通薄膜场效应晶体管; d）具有第一厚度的第一源极/漏极区域，第二源极/漏极区域具有第二厚度，沟道区域具有第三厚度; 第一和第二厚度中的至少一个大于第三厚度。公开了制造薄场效应晶体管的方法。

9. 发明授权

US06229212B1 Integrated circuitry and thin film transistors 有权
标题翻译：集成电路和薄膜晶体管
公开(公告)号：US06229212B1
公开(公告)日：2001-05-08
申请号：US09416818
申请日：1999-10-12
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L2348
CPC分类号： H01L29/6675 , H01L27/11 , H01L27/1108 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78648 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
摘要翻译：电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。这样可用于制造薄膜晶体管和其他电路。

10. 发明授权

US5858821A Method of making thin film transistors 失效
标题翻译：制造薄膜晶体管的方法
公开(公告)号：US5858821A
公开(公告)日：1999-01-12
申请号：US706641
申请日：1996-09-05
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786
CPC分类号： H01L29/66757 , H01L27/11 , H01L27/1108 , H01L29/78618
摘要： A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.
摘要翻译：薄膜场效应晶体管包括：a）薄膜沟道区; b）与薄膜通道区相邻的一对相对的导电的第一和第二源/漏区; c）栅极绝缘体和位于薄膜通道区域附近的栅极，用于对沟道区域进行电激励以导通薄膜场效应晶体管; d）具有第一厚度的第一源极/漏极区域，第二源极/漏极区域具有第二厚度，沟道区域具有第三厚度; 第一和第二厚度中的至少一个大于第三厚度。公开了制造薄场效应晶体管的方法。

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