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11. 发明授权

US07791210B2 Semiconductor package having discrete non-active electrical components incorporated into the package 有权
标题翻译：半导体封装具有并入封装中的离散非有源电气元件
公开(公告)号：US07791210B2
公开(公告)日：2010-09-07
申请号：US10702996
申请日：2003-11-05
申请人： Leah Miller , Aritharan Thurairajaratnam
发明人： Leah Miller , Aritharan Thurairajaratnam
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , H01L25/16 , H01L2224/16 , H01L2924/15173 , H01L2924/15311 , H01L2924/19105 , H01L2924/3025
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.
摘要翻译：本发明的实施例包括半导体集成电路封装，其包括具有附接到其上的集成电路管芯的衬底。衬底还包括至少一个具有形成在其上的多个电信号迹线的信号层。该封装包括安装在封装上的分立的非有源电气部件，使得集成电路管芯通过离散的非有源电气部件与封装的电信号迹线电连接。并且在一个特定实施方案中，分立的非有源电子部件包括串联布置在电信号迹线和裸片之间的电容元件，使得电容器作为封装安装的AC耦合电容器工作。

12. 发明授权

US07508062B2 Package configuration and manufacturing method enabling the addition of decoupling capacitors to standard package designs 失效
标题翻译：封装配置和制造方法能够将标准封装设计中的去耦电容加入
公开(公告)号：US07508062B2
公开(公告)日：2009-03-24
申请号：US11078052
申请日：2005-03-11
申请人： Leah Miller , Ivor Barber , Aritharan Thurairajaratnam
发明人： Leah Miller , Ivor Barber , Aritharan Thurairajaratnam
IPC分类号： H01L23/053 , H01L23/12
CPC分类号： H01L23/49822 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H05K1/0231 , H05K1/112 , H05K1/162 , H05K3/4644 , H05K3/4688 , H05K2201/09309 , H01L2924/00
摘要： The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.
摘要翻译：本发明涉及一种制造具有去耦电容器的集成电路封装的方法，所述去耦电容器使用构想为不使用去耦电容器的封装设计。该封装通过对原始设计的最小重新设计实现，而不需要重新设计信号迹线图案。本发明涉及用通孔带替换顶部和底部接合焊盘，然后用具有与下面的通孔带电连接的导电通孔的介电层覆盖顶部和底部参考平面。然后在电介质层上形成具有与下面参考平面相反极性的平面。这些平面包括与通孔对准的焊盘阵列。去耦电容器安装到封装的顶部，并与封装顶部的平面和紧靠的下面的参考平面电连接，而不通过与封装的信号平面通过的电容器的电连接。

13. 发明授权

US06825554B2 PBGA electrical noise isolation of signal traces 有权
标题翻译： PBGA电噪声隔离信号走线
公开(公告)号：US06825554B2
公开(公告)日：2004-11-30
申请号：US10387261
申请日：2003-03-11
申请人： Wee K. Liew , Aritharan Thurairajaratnam , Nadeem Haque
发明人： Wee K. Liew , Aritharan Thurairajaratnam , Nadeem Haque
IPC分类号： H01L2304
CPC分类号： H01L23/49816 , H01L23/49838 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A method for fabricating a semiconductor package having a 2-layer substrate, which includes an array of solder balls, is disclosed. The method includes patterning signal traces on a top layer of the substrate and identifying groups of signal traces to isolate. According to the present invention, a grounded isolation trace is then patterned adjacent to one of the groups of traces to isolate the signal traces, thereby providing noise shielding. In a preferred embodiment, the grounded isolation trace is provided with multiple vias, rather than only one. In a further aspect of the present invention a row of solder balls is connected together and to ground to create a bottom-layer isolating ground trace to further reduce noise. The bottom-layer isolating ground trace may be connected to the top-layer isolating ground trace using a via.
摘要翻译：公开了一种制造具有包括焊球阵列的2层基板的半导体封装的方法。该方法包括在衬底的顶层上构图信号迹线，并识别要隔离的信号迹线组。根据本发明，然后将接地隔离迹线图案化为与所述一组迹线相邻以隔离信号迹线，从而提供噪声屏蔽。在优选实施例中，接地隔离迹线设置有多个通孔，而不是只有一个。在本发明的另一方面，一排焊球连接在一起并接地以产生底层隔离接地迹线，以进一步降低噪声。底层隔离接地迹线可以使用通孔连接到顶层隔离接地迹线。

14. 发明授权

US07024637B2 Functionality based package design for integrated circuit blocks 有权
标题翻译：基于功能的集成电路块封装设计
公开(公告)号：US07024637B2
公开(公告)日：2006-04-04
申请号：US10673721
申请日：2003-09-29
申请人： Jeffrey A. Hall , Aritharan Thurairajaratnam
发明人： Jeffrey A. Hall , Aritharan Thurairajaratnam
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L2224/73204
摘要： A method of designing a packaged circuit, including a substrate and a circuit. The circuit is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known function and a known contact pattern. The circuit is designed by selecting desired functional blocks according to functions desired for the circuit. The substrate is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known contact pattern, a known signal trace routing layer pattern, a known ground plane layer pattern, and a known power plane layer pattern. A given one of the substrate functional blocks is associated with a given one of the circuit functional blocks. The substrate is designed by selecting substrate functional blocks associated with the desired ones of the circuit functional blocks.
摘要翻译：一种设计包括基板和电路的封装电路的方法。电路设计有多个标准化的功能块。每个功能块具有已知的功能和已知的接触图案。该电路根据电路所需的功能选择所需的功能块来设计。基板设计有多个标准化的功能块。每个功能块具有已知的接触图案，已知的信号迹线路由层图案，已知的接地平面图案图案和已知的功率平面图案图案。给定的一个基板功能块与给定的一个电路功能块相关联。通过选择与期望的电路功能块相关联的衬底功能块来设计衬底。

15. 发明授权

US06791177B1 Integrated circuit packaging that uses guard conductors to isolate noise-sensitive signals within the package substrate 有权
标题翻译：集成电路封装，其使用保护导体来隔离封装衬底内的噪声敏感信号
公开(公告)号：US06791177B1
公开(公告)日：2004-09-14
申请号：US10435805
申请日：2003-05-12
申请人： Leah M. Miller , Aritharan Thurairajaratnam , Edwin M. Fulcher
发明人： Leah M. Miller , Aritharan Thurairajaratnam , Edwin M. Fulcher
IPC分类号： H01L2352
CPC分类号： H05K1/0219 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K2201/09236 , H05K2201/09618 , H01L2924/00
摘要： A package substrate is contemplated herein for reducing cross-talk for noise-sensitive signals. The package substrate includes noise-sensitive conductors adapted to receive the noise-sensitive signals. In one embodiment, the cross-sectional width of the noise-sensitive conductors is increased to reduce certain parasitic effects such as resistance and/or inductance. The package substrate also includes guard conductors which are arranged co-planar with and substantially parallel to the noise-sensitive conductors. A plurality of vias spaced equidistant from one another extends from a ground conductor to the guard conductors, providing a substantially uniform voltage across the guard conductors. The overall effect will reduce the inductive and capacitive cross-talk from neighboring signals and increase the signal integrity of noise-sensitive signals.
摘要翻译：本文考虑的封装衬底用于减少噪声敏感信号的串扰。封装衬底包括适于接收噪声敏感信号的噪声敏感导体。在一个实施例中，噪声敏感导体的横截面宽度增加以减少某些寄生效应，例如电阻和/或电感。封装衬底还包括与噪声敏感导体共面并基本上平行的保护导体。彼此间隔开等距的多个通孔从接地导体延伸到保护导体，从而在保护导体上提供基本均匀的电压。整体效果将减少相邻信号的电感和电容串扰，并增加噪声敏感信号的信号完整性。

16. 发明授权

US06777803B2 Solder mask on bonding ring 有权
标题翻译：接合环上的焊接面罩
公开(公告)号：US06777803B2
公开(公告)日：2004-08-17
申请号：US10229659
申请日：2002-08-28
申请人： Maurice Othieno , Aritharan Thurairajaratnam , Manickam Thavarajah , Pradip D. Patei , Severino A. Legaspi, Jr.
发明人： Maurice Othieno , Aritharan Thurairajaratnam , Manickam Thavarajah , Pradip D. Patei , Severino A. Legaspi, Jr.
IPC分类号： H01L2352
CPC分类号： H01L23/49894 , H01L2924/0002 , H01L2924/00
摘要： An improvement to an integrated circuit package substrate of the type that has a bonding ring with an exposed upper surface, where a first portion of the exposed upper surface is for receiving a molding compound and a second portion of the exposed upper surface is for receiving an electrical connection. A solder mask is formed on the first portion of the exposed upper surface of the bonding ring.
摘要翻译：对具有暴露的上表面的接合环的类型的集成电路封装基板的改进，其中暴露的上表面的第一部分用于接收模制化合物，并且暴露的上表面的第二部分用于接收电气连接。在接合环的暴露的上表面的第一部分上形成焊料掩模。

17. 发明授权

US06717423B1 Substrate impedance measurement 有权
标题翻译：基板阻抗测量
公开(公告)号：US06717423B1
公开(公告)日：2004-04-06
申请号：US10267814
申请日：2002-10-09
申请人： Aritharan Thurairajaratnam , Mohan R. Nagar
发明人： Aritharan Thurairajaratnam , Mohan R. Nagar
IPC分类号： G01R3102
CPC分类号： G01R31/2805 , G01R1/07314 , G01R27/04
摘要： A probe structure with a connector connecting the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. A back side layer is connected to the connector. A probe side layer with contacts is sandwiched with the back side layer in a layered substrate. The probe side layer has a centrally disposed signal contact and surrounding ground contacts. A conductive layer is disposed between the back side layer and the probe side layer. The conductive layer is connected to the ground conductor of the connector and to the ground contacts of the probe side layer contacts. A via extends from the back side layer to the probe side layer. The via is connected to the signal conductor of the connector, and is also connected to the centrally disposed signal contact of the probe side layer contacts. The via does not make connection with the conductive layer. A first of pins is connected to the signal contact, for making a connection with a structure to be tested on the package substrate. Others of the pins are connected to the ground contacts, for making connections with structures on the package substrate that surround the structure to be tested.
摘要翻译：探针结构，其具有将探针结构连接到时域反射测试仪的连接器，其中连接器具有信号导体和接地导体。背面层连接到连接器。具有触点的探针侧层与层叠基板中的背面层夹持。探头侧层具有中心设置的信号触点和周围的接地触点。导电层设置在背侧层和探针侧层之间。导电层连接到连接器的接地导体和探头侧层触点的接地触头。通孔从背侧层延伸到探针侧层。通孔连接到连接器的信号导体，并且还连接到探头侧层触点的中心布置的信号触点。通孔不与导电层连接。第一个引脚连接到信号触点，用于与封装衬底上要测试的结构进行连接。其他引脚连接到接地触点，用于与围绕待测结构的封装基板上的结构进行连接。

18. 发明授权

US06555914B1 Integrated circuit package via 有权
标题翻译：集成电路封装通过
公开(公告)号：US06555914B1
公开(公告)日：2003-04-29
申请号：US09975871
申请日：2001-10-12
申请人： Aritharan Thurairajaratnam , Pradip D. Patel , Manickam Thavarajah , Hong T. Lim
发明人： Aritharan Thurairajaratnam , Pradip D. Patel , Manickam Thavarajah , Hong T. Lim
IPC分类号： H01L2352
CPC分类号： H05K1/116 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H05K3/429 , H05K2201/09545 , H05K2201/09718 , H01L2924/00
摘要： A method of forming a via in a circuit, such that parasitic capacitance is reduced. The surface layers of the circuit are identified, to which continuity with the via is desired, and secondary layers of the circuit are also identified. Via lands are formed only on the surface layers and not on the secondary layers. The via lands are formed in first portions of the surface layers, where the via is to pass through the surface layers. Nonconductive cut outs are formed in second portions of the secondary layers where the via is to pass through the secondary layers. The surface layers and the secondary layers of the circuit are laminated together. The first portions of the surface layers are aligned with the second portions of the secondary layers. A through hole is formed through the via lands formed in the surface layers, and also through the cut outs formed in the secondary layers. The via is formed in the through hole. The parasitic capacitance of the via is reduced by not having via lands on the secondary layers.
摘要翻译：一种在电路中形成通孔的方法，使得寄生电容减小。识别电路的表面层，对通孔的连续性是期望的，并且还识别电路的次级层。通常的焊盘只形成在表面层上，而不是在次级层上形成。通孔焊盘形成在表面层的第一部分中，其中通孔将通过表面层。在第二层的第二部分中形成非导电切口，其中通孔将通过次级层。电路的表面层和次级层叠在一起。表层的第一部分与第二层的第二部分对准。通过形成在表面层中的通孔接合区以及通过形成在次级层中的切口形成通孔。通孔形成在通孔中。通过在二级层上没有通孔焊盘来减小通孔的寄生电容。

19. 发明授权

US06534968B1 Integrated circuit test vehicle 失效
标题翻译：集成电路测试车
公开(公告)号：US06534968B1
公开(公告)日：2003-03-18
申请号：US09928071
申请日：2001-08-10
申请人： Leah M. Miller , Anand Govind , Zafer Kutlu , Chao-Wen Chung , Aritharan Thurairajaratnam
发明人： Leah M. Miller , Anand Govind , Zafer Kutlu , Chao-Wen Chung , Aritharan Thurairajaratnam
IPC分类号： G01R3100
CPC分类号： G01R31/04 , G01R31/2853 , G01R31/31716 , H05K1/0268 , H05K3/3436
摘要： An apparatus for detecting failures in electrical connections between an integrated circuit package substrate and a circuit board. The substrate has substrate electrical contacts that are electrically connected one to another in first sets in a first region of the substrate. The circuit board has circuit board electrical contacts that are electrically connected one to another in second sets in a second region of the circuit board. The substrate electrical contacts align with and make electrical contact with the circuit board electrical contacts. The first region of the substrate aligns with the second region of the circuit board when the substrate electrical contacts make electrical contact with the circuit board electrical contacts. The first sets of substrate electrical contacts form chains of electrical contacts with the second sets of circuit board electrical contacts. The chains of electrical contacts loop back and forth electrically between the substrate and the circuit board.
摘要翻译：一种用于检测集成电路封装衬底和电路板之间的电连接故障的装置。衬底具有在衬底的第一区域中的第一组中彼此电连接的衬底电触点。电路板具有在电路板的第二区域中在第二组中彼此电连接的电路板电触点。基板电触点与电路板电触点对齐并与之电接触。当基板电触头与电路板电触点电接触时，基板的第一区域与电路板的第二区域对齐。第一组基板电触点与第二组电路板电触点形成电触点链。电触头链在基板和电路板之间电连接。

20. 发明授权

US5903050A Semiconductor package having capacitive extension spokes and method for making the same 失效
标题翻译：具有电容性延伸辐条的半导体封装及其制造方法
公开(公告)号：US5903050A
公开(公告)日：1999-05-11
申请号：US070671
申请日：1998-04-30
申请人： Aritharan Thurairajaratnam , Wheling Cheng , Scott L. Kirkman
发明人： Aritharan Thurairajaratnam , Wheling Cheng , Scott L. Kirkman
IPC分类号： H01L23/64 , H01L23/52 , H01L23/48 , H01L23/495
CPC分类号： H01L23/642 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48233 , H01L2224/48235 , H01L2224/49 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/3011
摘要： Disclosed is a pair of conductive rings and method for making the conductive rings for introducing an integral network of capacitive structures around a semiconductor die of a semiconductor package. The pair of conductive rings include a ground rail ring that is defined around a semiconductor die pad that is configured to receive a semiconductor die. The ground rail ring has a first plurality of extension spokes that extend away from the ground rail ring. The pair of conductive rings further includes a power rail ring that is defined around the semiconductor die pad. The power rail ring has a second plurality of extension spokes that extend away from the power rail ring and toward the ground rail ring.
摘要翻译：公开了一对导电环和用于制造用于在半导体封装的半导体管芯周围引入电容结构的整体网络的导电环的方法。一对导电环包括限定在半导体管芯焊盘周围的接地导轨环，其被配置为接收半导体管芯。接地导轨环具有远离接地导轨环的第一多个延伸辐条。一对导电环还包括限定在半导体管芯焊盘周围的电源轨环。动力轨道环具有第二多个延伸辐条，其远离电力轨道环并且朝向地面轨道环延伸。

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