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11. 发明申请

US20180301119A1 System, Apparatus And Method For Increasing Performance In A Processor During A Voltage Ramp 审中-公开
公开(公告)号：US20180301119A1
公开(公告)日：2018-10-18
申请号：US15488662
申请日：2017-04-17
申请人： Altug Koker , Abhishek R. Appu , Bhushan M. Borole , Wenyin Fu , Kamal Sinha , Joydeep Ray
发明人： Altug Koker , Abhishek R. Appu , Bhushan M. Borole , Wenyin Fu , Kamal Sinha , Joydeep Ray
IPC分类号： G09G5/36
CPC分类号： G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G09G5/366 , G09G2310/066 , G09G2310/08 , G09G2340/02 , G09G2360/06 , G09G2360/08 , G09G2370/022 , G09G2370/16
摘要： In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

12. 发明申请

US20190261122A1 AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD 审中-公开
公开(公告)号：US20190261122A1
公开(公告)日：2019-08-22
申请号：US16269778
申请日：2019-02-07
申请人： Joydeep Ray , Travis T. Schluessler , Prasoonkumar Surti , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , James M. Holland , Jeffery S. Boles , Jonathan Kennedy , Louis Feng , Atsuo Kuwahara , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Mayuresh M. Varerkar
发明人： Joydeep Ray , Travis T. Schluessler , Prasoonkumar Surti , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , James M. Holland , Jeffery S. Boles , Jonathan Kennedy , Louis Feng , Atsuo Kuwahara , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Mayuresh M. Varerkar
IPC分类号： H04S7/00 , G09B21/00 , H04R1/40 , G06T15/06 , G06F3/01 , G06T1/20 , H04R3/00
摘要： Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

13. 发明申请

US20180300840A1 DISPLAY LINK COMPRESSION BY RENDER ENGINE 审中-公开
公开(公告)号：US20180300840A1
公开(公告)日：2018-10-18
申请号：US15488632
申请日：2017-04-17
申请人： Joydeep Ray , Prasoonkumar Surti , Abhishek R. Appu , Travis T. Schluessler , Linda L. Hurd , Eric J. Hoekstra
发明人： Joydeep Ray , Prasoonkumar Surti , Abhishek R. Appu , Travis T. Schluessler , Linda L. Hurd , Eric J. Hoekstra
IPC分类号： G06T1/20 , G06T15/00 , G06T1/60 , G09G5/39 , G09G5/00
摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to render data from an application to be displayed on a display panel, and a memory to store the compressed final display surface writes. The processor is to compress final display surface writes of the data to be displayed on the display panel in a format to be displayed on the display to allow a display engine coupled to the display to stream the compressed final display surface writes to the display.

14. 发明申请

US20180308201A1 COMPUTE OPTIMIZATION MECHANISM 审中-公开
公开(公告)号：US20180308201A1
公开(公告)日：2018-10-25
申请号：US15494905
申请日：2017-04-24
申请人： Abhishek R. Appu , Altug Koker , Linda L. Hurd , Dukhwan Kim , Mike B. Macpherson , John C. Weast , Feng Chen , Farshad Akhbari , Narayan Srinivasa , Nadathur Rajagopalan Satish , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman
发明人： Abhishek R. Appu , Altug Koker , Linda L. Hurd , Dukhwan Kim , Mike B. Macpherson , John C. Weast , Feng Chen , Farshad Akhbari , Narayan Srinivasa , Nadathur Rajagopalan Satish , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/3001 , G06F9/3017 , G06F9/3851 , G06F9/3887 , G06F9/3895 , G06F9/46 , G06N3/063 , G06T15/005 , G06T15/04 , G09G5/363
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.

15. 发明申请

US20180293701A1 APPARATUS AND METHOD FOR DYNAMIC PROVISIONING, QUALITY OF SERVICE, AND PRIORITIZATION IN A GRAPHICS PROCESSOR 审中-公开
公开(公告)号：US20180293701A1
公开(公告)日：2018-10-11
申请号：US15482680
申请日：2017-04-07
申请人： ABHISHEK R. APPU , Joydeep Ray , Altug Koker , Balaji Vembu , Pattabhiraman K , Matthew B. Callaway
发明人： ABHISHEK R. APPU , Joydeep Ray , Altug Koker , Balaji Vembu , Pattabhiraman K , Matthew B. Callaway
IPC分类号： G06T1/60 , G06T15/00 , G06F9/455 , G06F9/50 , G06F9/48
CPC分类号： G06T1/60 , G06F9/45558 , G06F9/4881 , G06F9/5038 , G06F2009/45579 , G06F2009/45591 , G06T15/005
摘要： An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

16. 发明授权

US10719917B2 On demand MSAA resolve during lens correction and/or other post-processing phases 有权
公开(公告)号：US10719917B2
公开(公告)日：2020-07-21
申请号：US16243490
申请日：2019-01-09
申请人： Tomer Bar-On , Hugues Labbe , Adam T. Lake , Kai Xiao , Ankur N. Shah , Johannes Guenther , Abhishek R. Appu , Joydeep Ray , Deepak S. Vembar , ElMoustapha Ould-Ahmed-Vall
发明人： Tomer Bar-On , Hugues Labbe , Adam T. Lake , Kai Xiao , Ankur N. Shah , Johannes Guenther , Abhishek R. Appu , Joydeep Ray , Deepak S. Vembar , ElMoustapha Ould-Ahmed-Vall
IPC分类号： G06T5/00 , G06T1/20 , G06T15/00 , G06T15/50 , G06T9/00 , G06T11/40
摘要： Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.

17. 发明申请

US20190251666A1 ON DEMAND MSAA RESOLVE DURING LENS CORRECTION AND/OR OTHER POST-PROCESSING PHASES 审中-公开
公开(公告)号：US20190251666A1
公开(公告)日：2019-08-15
申请号：US16243490
申请日：2019-01-09
申请人： Tomer Bar-On , Hugues Labbe , Adam T. Lake , Kai Xiao , Ankur N. Shah , Johannes Guenther , Abhishek R. Appu , Joydeep Ray , Deepak S. Vembar , ElMoustapha Ould-Ahmed-Vall
发明人： Tomer Bar-On , Hugues Labbe , Adam T. Lake , Kai Xiao , Ankur N. Shah , Johannes Guenther , Abhishek R. Appu , Joydeep Ray , Deepak S. Vembar , ElMoustapha Ould-Ahmed-Vall
IPC分类号： G06T5/00 , G06T11/40 , G06T9/00 , G06T15/50 , G06T1/20 , G06T15/00
CPC分类号： G06T5/002 , G06T1/20 , G06T9/00 , G06T11/40 , G06T15/005 , G06T15/503 , G06T2200/12
摘要： Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.

18. 发明申请

US20150169439A1 ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM 有权
标题翻译：在多级存储器系统中的异步代理数据引导
公开(公告)号：US20150169439A1
公开(公告)日：2015-06-18
申请号：US14133097
申请日：2013-12-18
申请人： Marc Torrant , David Puffer , Blaise Fanning , Bryan White , Joydeep Ray , Neil Schaper , Todd Witter , Altug Koker , Aditya Sreenivas
发明人： Marc Torrant , David Puffer , Blaise Fanning , Bryan White , Joydeep Ray , Neil Schaper , Todd Witter , Altug Koker , Aditya Sreenivas
IPC分类号： G06F12/02 , G06F12/08 , G06F12/10
CPC分类号： G06F12/126
摘要： A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.
摘要翻译：处理设备包括指令执行单元，存储器代理和钉住逻辑，以在存储器请求时针对多级存储器系统中的存储器页面进行引脚。钉扎逻辑包括代理接口模块，用于从存储器代理接收指示多级存储器系统中的第一存储器页的引脚请求，所述多级存储器系统包括近存储器和远存储器。钉扎逻辑还包括存储器接口模块，用于从远端存储器检索第一存储器页面，并将第一存储器页面写入近端存储器。此外，钉扎逻辑还包括描述符表管理模块，用于将第一存储器页标记为固定在近存储器中，其中将第一存储器页标记为固定包括将对应于第一存储器页的锁存位设置在高速缓存描述符表中并且当第一存储器页面被标记为被固定时，防止第一存储器页被从近存储器逐出。

19. 发明申请

US20180032431A1 Banking Graphics Processor Shared Local Memory 审中-公开
公开(公告)号：US20180032431A1
公开(公告)日：2018-02-01
申请号：US15219997
申请日：2016-07-26
申请人： Joydeep Ray , James A. Valerio , Abhishek R. Appu
发明人： Joydeep Ray , James A. Valerio , Abhishek R. Appu
IPC分类号： G06F12/06 , G06F9/38
CPC分类号： G06F12/0646 , G06F9/34 , G06F9/3824 , G06F9/3887
摘要： A graphics processor may be assigned a number of banks in a shared local memory to reduce the number of bank conflicts. In some cases, the number of banks may be higher than the single instruction multiple data slot number times the number of messages per cycle. The actual number of banks may be set to the next higher relatively prime number of 2n and 3 where n is 0-5.

20. 发明授权

US09600413B2 Common platform for one-level memory architecture and two-level memory architecture 有权
公开(公告)号：US09600413B2
公开(公告)日：2017-03-21
申请号：US14140261
申请日：2013-12-24
申请人： Joydeep Ray , Varghese George , Inder M. Sodhi , Jeffrey R. Wilcox
发明人： Joydeep Ray , Varghese George , Inder M. Sodhi , Jeffrey R. Wilcox
IPC分类号： G06F12/00 , G06F12/06 , G06F12/02 , G11C5/04
CPC分类号： G06F3/061 , G06F1/3287 , G06F3/0634 , G06F3/0655 , G06F3/0688 , G06F12/0246 , G06F12/0638 , G06F12/0811 , G06F15/781 , G06F2212/283 , G06F2212/7206 , G11C5/04
摘要： Technologies for one-level memory (1LM) and two-level memory (2LM) configurations in a common platform are described. A processor includes a first memory interface coupled to a first memory device that is located off-package of the processor and a second memory interface coupled to a second memory device that is located off-package of the processor. The processor also includes a multi-level memory controller (MLMC) coupled to the first memory interface and the second memory interface. The MLMC includes a first configuration and a second configuration. The first memory device is a random access memory (RAM) of a one-level memory (1LM) architecture in the first configuration. The first memory device is a first-level RAM of a two-level memory (2LM) architecture in the second configuration and the second memory device is a second-level non-volatile memory (NVM) of the 2LM architecture in the second configuration.

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