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    • 1. 发明申请
    • ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM
    • 在多级存储器系统中的异步代理数据引导
    • US20150169439A1
    • 2015-06-18
    • US14133097
    • 2013-12-18
    • Marc TorrantDavid PufferBlaise FanningBryan WhiteJoydeep RayNeil SchaperTodd WitterAltug KokerAditya Sreenivas
    • Marc TorrantDavid PufferBlaise FanningBryan WhiteJoydeep RayNeil SchaperTodd WitterAltug KokerAditya Sreenivas
    • G06F12/02G06F12/08G06F12/10
    • G06F12/126
    • A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.
    • 处理设备包括指令执行单元,存储器代理和钉住逻辑,以在存储器请求时针对多级存储器系统中的存储器页面进行引脚。 钉扎逻辑包括代理接口模块,用于从存储器代理接收指示多级存储器系统中的第一存储器页的引脚请求,所述多级存储器系统包括近存储器和远存储器。 钉扎逻辑还包括存储器接口模块,用于从远端存储器检索第一存储器页面,并将第一存储器页面写入近端存储器。 此外,钉扎逻辑还包括描述符表管理模块,用于将第一存储器页标记为固定在近存储器中,其中将第一存储器页标记为固定包括将对应于第一存储器页的锁存位设置在高速缓存描述符表中 并且当第一存储器页面被标记为被固定时,防止第一存储器页被从近存储器逐出。
    • 5. 发明授权
    • Low power display mode
    • 低功耗显示模式
    • US08314806B2
    • 2012-11-20
    • US11322880
    • 2006-04-13
    • Eric SamsonAditya NavaleTodd Witter
    • Eric SamsonAditya NavaleTodd Witter
    • G09G5/39
    • G06F3/14G09G5/006G09G5/008G09G5/363G09G5/39G09G2330/021
    • A controller is described that includes wiring to transport notification that a FIFO that holds data to be used to display content on a display has reached a threshold. The controller also includes first control circuitry to turn on a phase locked loop (PLL) circuit to cause logic circuitry within the controller downstream from the PLL to begin to receive a first clock in response to the notification. The logic circuitry is to transport data read from a memory toward the FIFO. The controller also includes second control circuitry to cause the memory to use a second clock provided by the controller in response to the notification.
    • 描述了一种控制器,其包括用于传送通知的连接,即在显示器上保存用于显示内容的数据的FIFO已经达到阈值。 该控制器还包括第一控制电路,用于接通锁相环(PLL)电路,以使PLL内的控制器内的逻辑电路响应该通知开始接收第一时钟。 逻辑电路是将从存储器读取的数据传输到FIFO。 控制器还包括第二控制电路,以使存储器响应于该通知使用由控制器提供的第二时钟。