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1. 发明申请

US20180308201A1 COMPUTE OPTIMIZATION MECHANISM 审中-公开
公开(公告)号：US20180308201A1
公开(公告)日：2018-10-25
申请号：US15494905
申请日：2017-04-24
申请人： Abhishek R. Appu , Altug Koker , Linda L. Hurd , Dukhwan Kim , Mike B. Macpherson , John C. Weast , Feng Chen , Farshad Akhbari , Narayan Srinivasa , Nadathur Rajagopalan Satish , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman
发明人： Abhishek R. Appu , Altug Koker , Linda L. Hurd , Dukhwan Kim , Mike B. Macpherson , John C. Weast , Feng Chen , Farshad Akhbari , Narayan Srinivasa , Nadathur Rajagopalan Satish , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/3001 , G06F9/3017 , G06F9/3851 , G06F9/3887 , G06F9/3895 , G06F9/46 , G06N3/063 , G06T15/005 , G06T15/04 , G09G5/363
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.

4. 发明申请

US20180285106A1 HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK 审中-公开
公开(公告)号：US20180285106A1
公开(公告)日：2018-10-04
申请号：US15477033
申请日：2017-04-01
申请人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
发明人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F9/30 , G06T15/00 , G06T1/60 , G06T1/20 , G06F9/46 , G09G5/36
摘要： In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

5. 发明申请

US20180300238A1 ADAPTIVE CACHE SIZING PER WORKLOAD 审中-公开
公开(公告)号：US20180300238A1
公开(公告)日：2018-10-18
申请号：US15488637
申请日：2017-04-17
申请人： Balaji Vembu , Altug Koker , Josh B. Mastronarde , Nikos Kaburlasos , Abhishek R. Appu , Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Pattabhiraman K , Kamal Sinha , Bhushan M. Borole , Wenyin Fu , Joydeep Ray , Prasoonkumar Surti , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
发明人： Balaji Vembu , Altug Koker , Josh B. Mastronarde , Nikos Kaburlasos , Abhishek R. Appu , Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Pattabhiraman K , Kamal Sinha , Bhushan M. Borole , Wenyin Fu , Joydeep Ray , Prasoonkumar Surti , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F12/06
摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.

6. 发明申请

US20180285158A1 HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS 审中-公开
公开(公告)号：US20180285158A1
公开(公告)日：2018-10-04
申请号：US15477026
申请日：2017-04-01
申请人： Abhishek R. Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
发明人： Abhishek R. Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
IPC分类号： G06F9/50 , G06T1/60 , G06T1/20 , G06T15/00 , G06F9/48 , G06F1/32
摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

7. 发明申请

US20180300840A1 DISPLAY LINK COMPRESSION BY RENDER ENGINE 审中-公开
公开(公告)号：US20180300840A1
公开(公告)日：2018-10-18
申请号：US15488632
申请日：2017-04-17
申请人： Joydeep Ray , Prasoonkumar Surti , Abhishek R. Appu , Travis T. Schluessler , Linda L. Hurd , Eric J. Hoekstra
发明人： Joydeep Ray , Prasoonkumar Surti , Abhishek R. Appu , Travis T. Schluessler , Linda L. Hurd , Eric J. Hoekstra
IPC分类号： G06T1/20 , G06T15/00 , G06T1/60 , G09G5/39 , G09G5/00
摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to render data from an application to be displayed on a display panel, and a memory to store the compressed final display surface writes. The processor is to compress final display surface writes of the data to be displayed on the display panel in a format to be displayed on the display to allow a display engine coupled to the display to stream the compressed final display surface writes to the display.

8. 发明申请

US20180308272A1 DEDICATED FIXED POINT BLENDING FOR ENERGY EFFICIENCY 审中-公开
公开(公告)号：US20180308272A1
公开(公告)日：2018-10-25
申请号：US15493195
申请日：2017-04-21
申请人： Abhishek R. Appu , Prasoonkumar Surti , Srivallaba Mysore , Subhajit Dasgupta , Hiroshi Akiba , Eric J. Hoekstra , Linda L. Hurd , Travis T. Schluessler , Daren J. Schmidt
发明人： Abhishek R. Appu , Prasoonkumar Surti , Srivallaba Mysore , Subhajit Dasgupta , Hiroshi Akiba , Eric J. Hoekstra , Linda L. Hurd , Travis T. Schluessler , Daren J. Schmidt
IPC分类号： G06T15/00 , G06F9/54 , G06F1/32 , G06T15/50
CPC分类号： G06T15/005 , G06T1/20 , G06T15/503
摘要： Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.

9. 发明授权

US11010953B2 Dedicated fixed point blending for energy efficiency 有权
公开(公告)号：US11010953B2
公开(公告)日：2021-05-18
申请号：US15493195
申请日：2017-04-21
申请人： Abhishek R. Appu , Prasoonkumar Surti , Srivallaba Mysore , Subhajit Dasgupta , Hiroshi Akiba , Eric J. Hoekstra , Linda L. Hurd , Travis T. Schluessler , Daren J. Schmidt
发明人： Abhishek R. Appu , Prasoonkumar Surti , Srivallaba Mysore , Subhajit Dasgupta , Hiroshi Akiba , Eric J. Hoekstra , Linda L. Hurd , Travis T. Schluessler , Daren J. Schmidt
IPC分类号： G06T15/00 , G06T15/50 , G06T1/20 , G06F1/3287 , G06F9/54
摘要： Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.

10. 发明授权

US6125334A Module-configurable full-chip power profiler 失效
标题翻译：模块可配置的全芯片功率分析仪
公开(公告)号：US6125334A
公开(公告)日：2000-09-26
申请号：US66620
申请日：1998-04-24
申请人： Linda L. Hurd
发明人： Linda L. Hurd
IPC分类号： G06F11/34 , G01R21/133 , G01R31/30 , G06F1/26 , G06F9/38 , G06F17/50 , G06F1/00
CPC分类号： G06F9/3885 , G01R21/133 , G01R31/3004 , G06F1/26 , G06F17/5022 , G06F9/3891 , G06F2217/78
摘要： A method for determining the power consumption, resulting from execution of a block of code, of an integrated circuit that includes a processor module and one or more other circuit modules. The method involves the steps of, first, providing a set of average current values for each of said modules, for a predetermined plurality of sets of conditions based on predetermined sets of signal line states associated with said module, for each instruction in the instruction set of said processor module, said sets of conditions being selected for dominant power consumption effect on the module. For each module, for each instruction in a block of code to be executed on said processor module, a set of signal line states is generated, associated with said module, for each processor cycle, in sequence. The generated set of signal line states are then tested for said set of conditions. One of said average current values is assigned for each condition so tested that is met. Finally, the running total of said average current values so met is accumulated for each such processor cycle. The average current values can be translated for different frequencies and supply voltages. Also, average current can be converted to average power consumption.
摘要翻译：一种用于确定包括处理器模块和一个或多个其它电路模块的集成电路的代码块执行所产生的功耗的方法。该方法包括以下步骤：首先，针对指令集中的每个指令，基于与所述模块相关联的预定的信号线状态组，为每个所述模块提供一组平均电流值，用于预定的多组条件所述处理器模块的所述条件选择用于对所述模块的主要功耗影响。对于每个模块，对于要在所述处理器模块上执行的代码块中的每个指令，依次为每个处理器周期生成与所述模块相关联的一组信号线状态。然后对所述条件集合测试生成的信号线状态集合。对所满足的每个条件进行测试分配所述平均电流值之一。最后，对于每个这样的处理器周期，累积所遇到的所述平均电流值的运行总和。平均电流值可以转换为不同的频率和电源电压。此外，平均电流可以转换为平均功耗。

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