会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 11. 发明申请
    • Nonvolatile Semiconductor Storing Device and Block Redundancy Saving Method
    • 非易失性半导体存储器件和块冗余保存方法
    • US20070279984A1
    • 2007-12-06
    • US10589101
    • 2005-02-09
    • Yasumichi MoriMasahiko Watanabe
    • Yasumichi MoriMasahiko Watanabe
    • G11C11/34
    • G11C29/76
    • A nonvolatile semiconductor storing device according to the present invention comprises a block replacing means for replacing a defective block with a redundant block when a memory block in a memory array is the defective block. The block replacing means includes an address translation circuit 10 for converting an inputted external block address into an internal block address by inverting an address bit corresponding to dissident of each address bit between a defective block address of the defective block and a redundant block address among address bits of the inputted external block address, and each of the memory blocks 5 is selected based on the internal block address after the translation of the external block address inputted from outside by the address translation circuit 10.
    • 根据本发明的非易失性半导体存储装置包括:块存储器替换装置,用于在存储器阵列中的存储块是缺陷块时用冗余块替换缺陷块。 块替换装置包括地址转换电路10,用于将输入的外部块地址转换为内部块地址,通过将与缺陷块的缺陷块地址和地址中的冗余块地址之间的每个地址位的不同位相对应的地址位反相 基于由地址转换电路10从外部输入的外部块地址的转换之后的内部块地址来选择输入的外部块地址的比特,并且存储块5中的每一个被选择。
    • 12. 发明授权
    • Reading circuit, reference circuit, and semiconductor memory device
    • 读取电路,参考电路和半导体存储器件
    • US06930922B2
    • 2005-08-16
    • US10630568
    • 2003-07-29
    • Yasumichi MoriTakahiko YoshimotoShinsuke AnzaiTakeshi Nojima
    • Yasumichi MoriTakahiko YoshimotoShinsuke AnzaiTakeshi Nojima
    • G11C16/06G11C7/00G11C11/56G11C16/02G11C16/04G11C16/28
    • G11C11/5642G11C16/28G11C2211/5634
    • A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.
    • 读取电路,用于从多个存储单元的一个存储单元读取数据,包括多个分割感测电路,每个分割感测电路经由多个感测线路中与之对应的感测线连接到该一个存储单元; 以及电流 - 电压转换电路,用于将流过每个感测线的电流转换成表示相应感测线的电位的感测电压。 每个分割感测电路包括用于经由相应的感测线路向一个存储单元提供电流的电流负载电路和用于感测相应感测线与多条参考线的对应参考线之间的电位差的读出放大器。 包括在至少一个分割感测电路中的电流负载电路具有与包括在另一个分割感测电路中的当前负载电路不同的电流供应能力。
    • 14. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US06912161B2
    • 2005-06-28
    • US10611643
    • 2003-07-02
    • Yasuaki HiranoYasumichi MoriShuichiro Kouchi
    • Yasuaki HiranoYasumichi MoriShuichiro Kouchi
    • G11C16/04G11C11/56G11C16/06G11C16/10G11C16/28
    • G11C11/5642G11C16/10G11C16/28G11C2211/5634
    • In the nonvolatile semiconductor memory device of this invention, a program control circuit 1 sets the threshold value of a first reference cell RFC0 by means of a write circuit WC on the basis of a result of comparing the threshold value of the first reference cell RFC0 with the threshold value of a second reference cell SRC executed by a sense amplifier 8 for trimming. The compare of threshold values by the sense amplifier 8 for trimming can be executed within a shorter time than in the threshold value read operation of the first reference cell RFC0. Therefore, when the number of the first reference cells is increased, the threshold value adjustment time can be remarkably reduced in comparison with the prior art in which the threshold value of the first reference cell is adjusted by reading the first reference cell.
    • 在本发明的非易失性半导体存储器件中,程序控制电路1基于比较第一参考单元RFC的阈值的结果,通过写入电路WC来设置第一参考单元RFC0的阈值 0与用于修整的读出放大器8执行的第二参考单元SRC的阈值。 可以在比第一参考单元RFC 0的阈值读取操作更短的时间内执行用于修整的读出放大器8的阈值的比较。因此,当第一参考单元的数量增加时,阈值 与通过读取第一参考单元来调整第一参考单元的阈值的现有技术相比,可以显着地减小调整时间。
    • 15. 发明授权
    • Non-volatile semiconductor memory device and information apparatus
    • 非易失性半导体存储器件和信息装置
    • US06751153B2
    • 2004-06-15
    • US10187048
    • 2002-06-28
    • Yasumichi MoriKen SumitaniYuji TanakaHaruyasu Fukui
    • Yasumichi MoriKen SumitaniYuji TanakaHaruyasu Fukui
    • G11C800
    • G11C8/12G11C16/08
    • A non-volatile semiconductor memory device, comprises a plurality of memory banks each including a plurality of memory cells, a command recognition section for identifying an externally input command signal and outputting an identification signal, an internal control section for generating a control signal for executing a command designated by the identification signal, an address control section for generating an internal address signal to a memory region including an arbitrary combination of the plurality of memory banks to be accessed, based on the externally input address signal, and a first address inversion section for inverting or non-inverting the logical values of at least a specific bit of the input address signal and outputting the resultant input address signal to the address control section. Predetermined memory cells are accessed based on the control signal and the internal address signal.
    • 一种非易失性半导体存储器件,包括多个存储单元,每个存储单元包括多个存储器单元,用于识别外部输入的命令信号并输出​​识别信号的命令识别单元,用于产生用于执行的控制信号的内部控制单元 由识别信号指定的命令,地址控制部分,用于根据外部输入的地址信号,向包括要访问的多个存储体组的任意组合的存储区域产生内部地址信号;以及第一地址转换部分 用于反相或非反相输入地址信号的至少一个特定位的逻辑值,并将结果输入地址信号输出到地址控制部分。 基于控制信号和内部地址信号来访问预定的存储单元。
    • 16. 发明授权
    • Data transfer control device, semiconductor memory device and electronic information apparatus
    • 数据传输控制装置,半导体存储装置和电子信息装置
    • US06646947B2
    • 2003-11-11
    • US10184133
    • 2002-06-26
    • Haruyasu FukuiKen SumitaniYasumichi Mori
    • Haruyasu FukuiKen SumitaniYasumichi Mori
    • G11C700
    • G06F13/28
    • A data transfer control device of the present invention includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section.
    • 本发明的数据传输控制装置包括:用于识别输入控制命令的命令识别部分; 第一地址输出部分,用于基于输入的控制命令来控制数据传送地址的输出和存储顺序以及数据传送完成地址; 第一存储器地址存储部分,用于存储从第一地址输出部分输出的第一存储器阵列的数据传输开始地址; 第二存储器地址存储部分,用于存储从第一地址输出部分输出的第二存储器阵列的数据传输开始地址; 第三存储器地址存储部分,用于存储从第一地址输出部分输出的数据传输完成地址。
    • 17. 发明授权
    • Nonvolatile semiconductor storing device and block redundancy saving method
    • 非易失性半导体存储器件和块冗余保存方法
    • US07460419B2
    • 2008-12-02
    • US10589101
    • 2005-02-09
    • Yasumichi MoriMasahiko Watanabe
    • Yasumichi MoriMasahiko Watanabe
    • G11C29/00G11C7/00
    • G11C29/76
    • A nonvolatile semiconductor storing device according to the present invention comprises a block replacing means for replacing a defective block with a redundant block when a memory block in a memory array is the defective block. The block replacing means includes an address translation circuit 10 for converting an inputted external block address into an internal block address by inverting an address bit corresponding to dissident of each address bit between a defective block address of the defective block and a redundant block address among address bits of the inputted external block address, and each of the memory blocks 5 is selected based on the internal block address after the translation of the external block address inputted from outside by the address translation circuit 10.
    • 根据本发明的非易失性半导体存储装置包括:块存储器替换装置,用于在存储器阵列中的存储块是缺陷块时用冗余块替换缺陷块。 块替换装置包括地址转换电路10,用于将输入的外部块地址转换为内部块地址,通过将与缺陷块的缺陷块地址和地址中的冗余块地址之间的每个地址位的不同位相对应的地址位反相 基于由地址转换电路10从外部输入的外部块地址的转换之后的内部块地址来选择输入的外部块地址的比特,并且存储块5中的每一个被选择。
    • 18. 发明授权
    • Semiconductor storage device
    • 半导体存储设备
    • US07430144B2
    • 2008-09-30
    • US10589066
    • 2005-02-09
    • Masahiko WatanabeYasumichi Mori
    • Masahiko WatanabeYasumichi Mori
    • G11C7/00
    • G11C8/12G11C16/08G11C16/28G11C29/76G11C29/82
    • A semiconductor storage device according to the present invention comprises one or more memory planes 8 comprising a plurality of memory blocks 9, and a block selection circuit for decoding an block address signal for selecting the memory block 9 from the memory plane 8 to select the memory block, generates a dummy block address for selecting a dummy block that is different from the selected block address and a defective block address of a defective block by a predetermined logical operation targeted for a specific partial bit in address bits of the selected block address when the defective block is contained in the memory plane. A bit line connected to the selected memory cell selected by the selected block address and a bit line in the dummy block are connected to differential input terminals of a sense amplifier circuit 9.
    • 根据本发明的半导体存储装置包括一个或多个包括多个存储器块9的存储器平面8和一个块选择电路,用于解码用于从存储器平面8中选择存储器块9的块地址信号,以选择存储器 块,产生一个虚拟块地址,用于当所选择的块地址的地址位中的特定部分位的目标地址为预定逻辑运算时,选择不同于所选择的块地址的虚拟块和缺陷块的缺陷块地址, 缺陷块包含在存储器平面中。 连接到由选择的块地址选择的所选存储单元的位线和伪块中的位线连接到读出放大器电路9的差分输入端。
    • 20. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US06661692B2
    • 2003-12-09
    • US10179710
    • 2002-06-24
    • Shinsuke AnzaiKenji KameiYasumichi Mori
    • Shinsuke AnzaiKenji KameiYasumichi Mori
    • G11C506
    • G11C29/80G11C15/00G11C15/046H01L27/0207
    • A semiconductor integrated circuit of the present invention includes: n first output circuits and m second output circuits which are provided such that adjacent first and second output circuits are spaced at a regular first pitch; and input circuits which are provided such that adjacent input circuits are spaced at a regular second pitch, in which the first and second output circuits are provided such that at least part of ones of the first and second output circuit blocks alternate with the other ones of the first and second output circuits and each of the first output circuits is connected to a corresponding one of input circuits by a first conductor line which is kept straight, and second conductor lines are connected to the second output circuits such that each second conductor line passes through a gap between the input circuits.
    • 本发明的半导体集成电路包括:n个第一输出电路和m个第二输出电路,其被设置成使得相邻的第一和第二输出电路以规则的第一间距间隔开; 以及输入电路,其被设置为使得相邻输入电路以规则的第二间距间隔开,其中第一和第二输出电路被设置成使得第一和第二输出电路块中的至少一部分与其他 第一和第二输出电路和第一输出电路中的每一个通过保持直的第一导体线连接到相应的一个输入电路,并且第二导体线连接到第二输出电路,使得每个第二导线通过 通过输入电路之间的间隙。