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    • 13. 发明授权
    • Method for composing addresses of a memory
    • 构成存储器地址的方法
    • US4603348A
    • 1986-07-29
    • US460286
    • 1983-01-24
    • Mitsuhiko YamadaTsukasa NishidaToshifumi Inoue
    • Mitsuhiko YamadaTsukasa NishidaToshifumi Inoue
    • G11C7/00G06F12/06G06T1/60G11C8/00H04N1/46
    • G11C8/00
    • A method for subdividing the addresses of a multi-dimensional memory, having n-dimensional addresses defined over a logical address space which is divided into a plurality of unit divisions. Each unit division has several vertices each of which is addressable by one of the n-dimensional addresses. Each one of the addresses associated with a given unit division is divided and allocated to a distinct memory bank so that no two addresses of the same unit division are in the same memory bank. There are a total of 2.sup.n memory banks, each having independent data lines and address lines. The original n-dimensional address of the vertices determines to which memory bank the vertex address will be allocated. Moreover, the n-dimensional address also determines the address of the given vertex within the memory bank to which it has been allocated. Thus, the data corresponding to all the vertices of a given unit division can be accessed simultaneously to thereby significantly reduce data retrieval times in many applications.
    • 一种用于细分多维存储器的地址的方法,其具有在被划分成多个单位分区的逻辑地址空间上定义的n维地址。 每个单元划分具有多个顶点,每个顶点可由n维地址之一寻址。 与给定单元划分相关联的每个地址被划分并分配给不同的存储体,使得相同单位划分的两个地址不在同一个存储体中。 共有2n个存储体,每个存储体都具有独立的数据线和地址线。 顶点的原始n维地址确定将分配顶点地址的哪个存储区。 此外,n维地址还确定其已经被分配到的存储体内的给定顶点的地址。 因此,可以同时访问对应于给定单元划分的所有顶点的数据,从而在许多应用中显着减少数据检索时间。
    • 18. 发明授权
    • Method of and apparatus for compressing image data
    • 压缩图像数据的方法和装置
    • US4764975A
    • 1988-08-16
    • US897760
    • 1986-08-05
    • Toshifumi Inoue
    • Toshifumi Inoue
    • G06F3/14G06T3/40G09G5/36H04N1/393G06K9/36
    • G06T3/40H04N1/3935
    • The present invention relates to image data compression utilized either when an original image is displayed on a monitor or when an original is reproduced with a desired reduction ratio. Pixel data of an original image are sequentially inputted synchronously with a clock signal (CY), and an average value of pixel data inputted theretofore is renewed in an averaging circuit (40) each time pixel data are inputted. The renewal of the average value is repeated until an assignment signal (CX) is outputted from a DDA circuit (30). The assignment signal assigns pixels of the original image to the same number of blocks as the number of pixels of a desired compressed image, which is adapted for a desired image compression. An output obtained from the averaging circuit (40) represents an average value of pixel data with respect to each block aligned in the vertical direction of the original image. In a DDA circuit (50) an assignment for blocks in the horizontal direction of the original is carried out. Average values of pixel data with respect to each block adaptable for the desired image compression are obtained by an averaging circuit ( 60), which average values are used as pixel data of each pixel of the compression image.
    • PCT No.PCT / JP85 / 00671 Sec。 371日期:1986年8月5日 102(e)日期1986年8月5日PCT提交1985年12月6日PCT公布。 出版物WO86 / 03610 日期:1986年6月19日。本发明涉及当在监视器上显示原始图像时或当以期望的缩小比率再现原件时所使用的图像数据压缩。 原始图像的像素数据与时钟信号(CY)同步地顺序地输入,并且每当输入像素数据时,在平均电路(40)中更新输入的像素数据的平均值。 重复平均值的更新,直到从DDA电路(30)输出分配信号(CX)。 分配信号将原始图像的像素分配给与适合于期望的图像压缩的期望压缩图像的像素数相同的块数。 从平均电路(40)获得的输出表示相对于在原始图像的垂直方向上排列的每个块的像素数据的平均值。 在DDA电路(50)中,执行原稿的水平方向上的块的分配。 通过平均电路(60)获得相对于适用于期望图像压缩的每个块的像素数据的平均值,该平均值被用作压缩图像的每个像素的像素数据。