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11. 发明申请

US20090079004A1 METHOD FOR MAKING A TRANSISTOR WITH SELF-ALIGNED DOUBLE GATES BY REDUCING GATE PATTERNS 审中-公开
标题翻译：通过减少栅格图形制造具有自对准双门的晶体管的方法
公开(公告)号：US20090079004A1
公开(公告)日：2009-03-26
申请号：US11561174
申请日：2006-11-17
申请人： Christophe LICITRA , Maud Vinet
发明人： Christophe LICITRA , Maud Vinet
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66636 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/66772 , H01L29/78618
摘要： This invention relates to an improved microelectronic method for making a double gate structure for a transistor, and particularly gate patterns (108a,128a,208a,228a,308a,328a) with a critical dimension less than the critical dimension of the transistor channel zone (104b). This method particularly includes a step to reduce double gate patterns, using isotropic etching. The invention also relates to a microelectronic device obtained using such a method.
摘要翻译：本发明涉及一种用于制造用于晶体管的双栅极结构的改进的微电子方法，特别是具有临界尺寸小于晶体管沟道区的临界尺寸的栅极图案（108a，128a，208a，228a，308a，328a） 104b）。该方法特别包括使用各向同性蚀刻来减少双栅极图案的步骤。本发明还涉及使用这种方法获得的微电子器件。

12. 发明申请

US20070173064A1 Manufacturing process for a transistor made of thin layers 有权
标题翻译：由薄层制成的晶体管的制造工艺
公开(公告)号：US20070173064A1
公开(公告)日：2007-07-26
申请号：US11223089
申请日：2005-09-09
申请人： Maud Vinet , Pascal Besson , Bernard Previtali , Christian Vizioz
发明人： Maud Vinet , Pascal Besson , Bernard Previtali , Christian Vizioz
IPC分类号： C23F1/00 , H01L21/302 , H01L21/461 , C03C25/68
CPC分类号： H01L29/4908 , H01L29/66772
摘要： A process for fabricating a transistor comprising a gate (50′) located in the immediate proximity of a dielectric (46) includes a step of etching a layer of gate material. This gate etching step comprises the following steps: plasma etching of this layer over the major portion of its thickness so as to laterally define the gate (50′); chemical etching of a residual portion (48′) of this layer so as to define this gate as far as the dielectric (46).
摘要翻译：一种用于制造晶体管的工艺，其包括位于电介质（46）附近的栅极（50'），其包括蚀刻栅极材料层的步骤。该栅极蚀刻步骤包括以下步骤：在其厚度的主要部分上等离子体蚀刻该层，以横向限定栅极（50'）; 对该层的残留部分（48'）进行化学蚀刻，以便将该栅极限定为电介质（46）。

13. 发明授权

US09768055B2 Isolation regions for SOI devices 有权
公开(公告)号：US09768055B2
公开(公告)日：2017-09-19
申请号：US13590836
申请日：2012-08-21
申请人： Qing Liu , Nicolas Loubet , Prasanna Khare , Shom Ponoth , Maud Vinet , Bruce Doris
发明人： Qing Liu , Nicolas Loubet , Prasanna Khare , Shom Ponoth , Maud Vinet , Bruce Doris
IPC分类号： H01L21/76 , H01L21/762 , H01L29/66 , H01L29/786
CPC分类号： H01L21/76232 , H01L29/66772 , H01L29/78654
摘要： An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

14. 发明申请

US20150294903A1 METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS 有权
标题翻译：用于在有源区域部分地形成隔离斜面的微电子器件制造方法
公开(公告)号：US20150294903A1
公开(公告)日：2015-10-15
申请号：US14425891
申请日：2012-09-05
申请人： Laurent Grenouillet , Yannick Le Tiec , Nicolas Loubet , Maud Vinet , Romain Wacquez
发明人： Laurent Grenouillet , Yannick Le Tiec , Nicolas Loubet , Maud Vinet , Romain Wacquez
IPC分类号： H01L21/762 , H01L21/306 , H01L21/265 , H01L21/84
CPC分类号： H01L21/76283 , H01L21/26506 , H01L21/26586 , H01L21/30604 , H01L21/3065 , H01L21/3086 , H01L21/76224 , H01L21/76232 , H01L21/84
摘要： A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.
摘要翻译：一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层，注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下方延伸，用电介质材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括在有源区域的一部分下延伸的部分。

15. 发明授权

US09123814B2 Field effect device provided with a thinned counter-electrode and method for fabricating 有权
标题翻译：具有减薄的对电极的场效应器件和制造方法
公开(公告)号：US09123814B2
公开(公告)日：2015-09-01
申请号：US13352784
申请日：2012-01-18
申请人： Laurent Grenouillet , Maud Vinet
发明人： Laurent Grenouillet , Maud Vinet
IPC分类号： H01L27/12 , H01L29/786 , H01L21/265 , H01L29/66
CPC分类号： H01L29/78603 , H01L21/26586 , H01L29/66772 , H01L29/78648
摘要： A field effect device comprises a substrate of semiconductor on insulator type successively provided with a support substrate, an electrically insulating layer and a semiconductor material film. First and second source/drain electrodes are formed in the semiconductor material layer. A conduction channel is formed in the semiconductor material layer and separates the first and second source/drain electrodes. A counter-electrode is formed in the support substrate and faces the first and second source/drain electrodes and the conduction channel. The counter-electrode is formed by a doped area of the support substrate having a first doping impurity concentration which decreases from an interface between the electrically insulating layer and the support substrate.
摘要翻译：场效应器件包括连续设置有支撑衬底的绝缘体半导体衬底，电绝缘层和半导体材料膜。第一和第二源极/漏极形成在半导体材料层中。在半导体材料层中形成导电沟道，并分离第一和第二源极/漏极。在支撑基板上形成对置电极并面对第一和第二源/漏电极和导电沟道。对电极由支撑衬底的掺杂区域形成，其具有从电绝缘层和支撑衬底之间的界面减小的第一掺杂杂质浓度。

16. 发明申请

US20140054699A1 ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM OXIDE LINER AND UPPER NITRIDE LINER AND RELATED METHODS 有权
标题翻译：电子器件包括具有底部氧化物衬里和上层衬里的浅层隔离（STI）区域及相关方法
公开(公告)号：US20140054699A1
公开(公告)日：2014-02-27
申请号：US13590836
申请日：2012-08-21
申请人： QING LIU , PRASANNA KHARE , NICOLAS LOUBET , SHOM PONOTH , MAUD VINET , BRUCE DORIS
发明人： QING LIU , PRASANNA KHARE , NICOLAS LOUBET , SHOM PONOTH , MAUD VINET , BRUCE DORIS
IPC分类号： H01L27/12 , H01L21/76 , H01L29/00
CPC分类号： H01L21/76232 , H01L29/66772 , H01L29/78654
摘要： An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.
摘要翻译：电子器件可以包括衬底，覆盖衬底的掩埋氧化物（BOX）层，覆盖BOX层的至少一个半导体器件，以及衬底中的至少一个浅沟槽隔离（STI）区域，并且与至少一个半导体设备。所述至少一个STI区域限定具有衬底的侧壁表面，并且可以包括衬在侧壁表面的底部的氧化层，衬在底部上方的侧壁表面的顶部的氮化物层和氮化物和氧化物层。

17. 发明申请

US20120187489A1 FIELD EFFECT DEVICE PROVIDED WITH A LOCALIZED DOPANT DIFFUSION BARRIER AREA AND FABRICATION METHOD 有权
标题翻译：具有本地化多普勒扩散障碍区域和制造方法的场效应器件
公开(公告)号：US20120187489A1
公开(公告)日：2012-07-26
申请号：US13356975
申请日：2012-01-24
申请人： Laurent GRENOUILLET , Yannick LE TIEC , Nicolas POSSEME , Maud VINET
发明人： Laurent GRENOUILLET , Yannick LE TIEC , Nicolas POSSEME , Maud VINET
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78618 , H01L21/26586 , H01L29/66772 , H01L29/78696
摘要： The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.
摘要翻译：场效应器件包括牺牲栅极电极，其侧壁由形成在半导体材料膜上的横向间隔件覆盖。源极/漏极形成在半导体材料膜中并且布置在栅电极的每一侧上。扩散阻挡元件通过由牺牲栅极留下的空隙注入，以便在侧向间隔物下方形成修改的扩散区域。改性扩散区域是与源/漏电极相比掺杂杂质的迁移率降低的区域。

18. 发明授权

US08021934B2 Method for making a transistor with metallic source and drain 有权
标题翻译：制造具有金属源极和漏极的晶体管的方法
公开(公告)号：US08021934B2
公开(公告)日：2011-09-20
申请号：US12433209
申请日：2009-04-30
申请人： Maud Vinet , Thierry Poiroux , Bernard Previtali
发明人： Maud Vinet , Thierry Poiroux , Bernard Previtali
IPC分类号： H01L21/8232
CPC分类号： H01L29/41783 , H01L21/823814 , H01L29/41766 , H01L29/517 , H01L29/66628 , H01L29/66636 , H01L29/66643 , H01L29/66772 , H01L29/7834 , H01L29/7839 , H01L29/78648
摘要： A method including: making a structure on a substrate, said structure comprising at least a portion of a semiconductor material forming a channel of a field effect transistor, a gate located on the channel; forming at least one dielectric portion completely covering said structure and zones of the substrate corresponding to locations of a source and a drain of the field effect transistor; making two holes in the dielectric portion on each side of said structure, such that the locations of the source and the drain form bottom walls of the two holes and sides of the channel are exposed; depositing a first metallic layer on at least the bottom walls of the two holes, at least covering said sides of the channel; and depositing a second metallic layer on the first metallic layer-to form the source and the drain of the field effect transistor.
摘要翻译：一种方法，包括：在衬底上形成结构，所述结构包括形成场效应晶体管的沟道的半导体材料的至少一部分，位于沟道上的栅极; 形成至少一个电介质部分，完全覆盖对应于场效应晶体管的源极和漏极的位置的所述结构和衬底的区域; 在所述结构的每一侧的电介质部分中形成两个孔，使得源和漏极形成两个孔的底壁和通道的侧面的位置被暴露; 在至少两个孔的底壁上沉积第一金属层，至少覆盖通道的所述侧面; 以及在第一金属层上沉积第二金属层，以形成场效应晶体管的源极和漏极。

19. 发明授权

US07973350B2 Strained-channel transistor device 有权
标题翻译：应变通道晶体管器件
公开(公告)号：US07973350B2
公开(公告)日：2011-07-05
申请号：US12152353
申请日：2008-05-13
申请人： Michael Collonge , Maud Vinet
发明人： Michael Collonge , Maud Vinet
IPC分类号： H01L21/02
CPC分类号： H01L29/78654 , H01L29/66772 , H01L29/7843 , H01L29/78696
摘要： Semiconductor device comprising at least: one substrate, a transistor comprising at least one source region, one drain region, one channel and one gate, a planar layer based on at least one piezoelectric material, resting at least on the gate and capable of inducing at least mechanical strain on the transistor channel, in a direction that is substantially perpendicular to the plane of a face of the piezoelectric layer situated on the gate side, the piezoelectric layer being arranged between two biasing electrodes, one of the two biasing electrodes being formed by a first layer based on at least one electrically conductive material such that the piezoelectric layer is arranged between this first conductive layer and the gate of the transistor.
摘要翻译：半导体器件至少包括：一个衬底，包括至少一个源极区，一个漏极区，一个沟道和一个栅极的晶体管，基于至少一个压电材料的平面层，至少搁在栅极上并能够诱导晶体管沟道上的最小的机械应变在基本上垂直于位于栅极侧的压电层的面的平面的方向上，压电层设置在两个偏置电极之间，两个偏置电极之一由基于至少一种导电材料的第一层，使得压电层布置在该第一导电层和晶体管的栅极之间。

20. 发明授权

US07829916B2 Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor 有权
标题翻译：具有由栅电极封装的锗基通道的晶体管和用于制造这种晶体管的方法
公开(公告)号：US07829916B2
公开(公告)日：2010-11-09
申请号：US11920835
申请日：2006-05-23
申请人： Yves Morand , Thierry Poiroux , Maud Vinet
发明人： Yves Morand , Thierry Poiroux , Maud Vinet
IPC分类号： H01L29/66 , H01L21/44
CPC分类号： H01L29/785 , H01L29/42392
摘要： Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.
摘要翻译：源电极和漏电极各自由锗和硅化合物制成的第一和第二层的交替形成。第一层的锗浓度介于0％和10％之间，第二层的锗浓度在10％至50％之间。至少一个通道分别连接源电极和漏电极的两个第二层。该方法包括以层叠的方式蚀刻通过窄带连接的源区和漏区。然后执行所述堆叠的表面热氧化，以便使锗浓度在10％至50％之间的锗和硅化合物的硅氧化并使锗Ge冷凝。去除窄区域的氧化硅，并且在狭窄区域的浓缩锗上沉积栅极电介质和栅极。

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