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11. 发明授权

US06237081B1 Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor 失效
标题翻译：排队方法和装置，用于便于在处理器中拒绝顺序指令
公开(公告)号：US06237081B1
公开(公告)日：2001-05-22
申请号：US09213319
申请日：1998-12-16
申请人： Hung Qui Le , Larry Edward Thatcher , Bruce Joseph Ronchetti , David James Shippy
发明人： Hung Qui Le , Larry Edward Thatcher , Bruce Joseph Ronchetti , David James Shippy
IPC分类号： G06F932
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861
摘要： A processor (100) includes an issue unit (125) having an issue queue (144) for issuing instructions to an execution unit (140). The execution unit (140) may accept and execute the instruction or produce a reject signal. After each instruction is issued, the issue queue (144) retains the issued instruction for a critical period. After the critical period, the issue queue (144) may drop the issued instruction unless the execution unit (140) has generated a reject signal. If the execution unit (140) has generated a reject signal, the instruction is eventually marked in the issue queue (144) as being available to be reissued. The length of time that the rejected instruction is held from reissue may be modified depending upon the nature of the rejection by the execution unit (140). Also, the execution unit (140) may conduct corrective actions in response to certain reject conditions so that the instruction may be fully executed upon reissue.
摘要翻译：处理器（100）包括具有用于向执行单元（140）发出指令的发布队列（144）的发布单元（125）。执行单元（140）可接受并执行该指令或产生拒绝信号。在发出每条指令之后，发出队列（144）保留发出的关键周期指令。在关键时段之后，发布队列（144）可以放弃发出的指令，除非执行单元（140）已经产生了拒绝信号。如果执行单元（140）已经产生了拒绝信号，则指令最终在发布队列（144）中被标记为可重新发行。可以根据执行单元（140）的拒绝的性质来修改拒绝指令从重新发行保持的时间长度。此外，执行单元（140）可以响应于某些拒绝条件进行校正动作，使得可以在重新发布时完全执行该指令。

12. 发明授权

US6021467A Apparatus and method for processing multiple cache misses to a single cache line 失效
标题翻译：用于处理多个高速缓存未命中到单个高速缓存行的装置和方法
公开(公告)号：US6021467A
公开(公告)日：2000-02-01
申请号：US713056
申请日：1996-09-12
申请人： Brian R. Konigsburg , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
发明人： Brian R. Konigsburg , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0859 , G06F12/0897 , Y02B60/1225
摘要： An apparatus and method for processing multiple cache misses to a single cache line in an information handling system which includes a miss queue for storing requests for data not located in a level one cache and a comparator for comparing requests for data stored in the miss queue to determine if there are multiple requests for data located in the same cache line of a level two cache. Each new request for data from the same cache line of the level two cache as an older original request for data in the miss queue is marked as a load hit reload. The requests marked as load hit reloads are then grouped together with the matching original request and forwarded together to the level two cache wherein the original request requests the data from level two cache. The load hit reload requests do not access level two cache but instead bypass access of level two cache by extracting data from the cache line outputted from level two cache for the matching original request. The present invention reduces the number of accesses to the level two cache and allows data requests to be satisfied in parallel versus serially when multiple successive level one cache misses occur.
摘要翻译：一种用于处理信息处理系统中的多个高速缓存未命中到单个高速缓存行的装置和方法，该信息处理系统包括用于存储不在一级高速缓存中的数据的请求的未命中队列，以及比较器，用于将存储在所述未命中队列中的数据的请求与确定是否存在针对二级缓存的同一高速缓存行中的数据的多个请求。来自与二级缓存相同的高速缓存行的数据的新请求作为旧队列中的数据的较早原始请求被标记为加载命中重新加载。标记为加载命中重载的请求随后与匹配的原始请求分组在一起并一起转发到二级缓存，其中原始请求请求来自二级缓存的数据。加载命中重新加载请求不访问二级缓存，而是通过从匹配的原始请求的二级缓存输出的高速缓存行中提取数据来绕过二级缓存的访问。本发明减少对二级高速缓存的访问次数，并且允许当发生多个连续一级高速缓存未命中时并行地对数据请求进行满足。

13. 发明授权

US5974259A Data processing system and method of operation having input/output drivers with reduced power consumption and noise levels 失效
标题翻译：具有输入/输出驱动器的数据处理系统和操作方法具有降低的功耗和噪声水平
公开(公告)号：US5974259A
公开(公告)日：1999-10-26
申请号：US715694
申请日：1996-09-18
申请人： Humberto Felipe Casal , Kurt Alan Feiste , T. W. Griffith, Jr. , Larry Edward Thatcher
发明人： Humberto Felipe Casal , Kurt Alan Feiste , T. W. Griffith, Jr. , Larry Edward Thatcher
IPC分类号： G06F1/10 , G06F13/42 , G06F1/00 , G06F1/04
CPC分类号： G06F13/4243 , G06F1/10 , Y02B60/1228 , Y02B60/1235
摘要： A data processing system has a memory bus and a system input/output (I/O) bus including I/O drivers. The memory and I/O buses are controlled by a central processor unit (CPU) for transferring data therebetween and to the I/O drivers. A central clock provides clock signals to the CPU, the memory bus and the I/O bus. The central clock further provides memory and I/O phase alignment signals to the CPU, the alignment signals indicating to the CPU when the start of the CPU clock cycle coincides with the start of a memory bus clock cycle or I/O bus clock signal. Circuit means responsive to the phase alignment and CPU clock signals initiate the transfer of data to the memory and I/O data buses in alternate CPU clock signals to reduce the number of I/O pin switching at any given time thereby reducing the noise and power consumption at the I/O pins and in the system.
摘要翻译：数据处理系统具有存储器总线和包括I / O驱动器的系统输入/输出（I / O）总线。存储器和I / O总线由用于在其间传送数据的I / O驱动器的中央处理器单元（CPU）控制。中央时钟向CPU，存储器总线和I / O总线提供时钟信号。中央时钟还向CPU提供存储器和I / O相位对准信号，当CPU时钟周期的开始与存储器总线时钟周期或I / O总线时钟信号的开始一致时，向CPU指示的对准信号。响应于相位对准的电路装置和CPU时钟信号在备用CPU时钟信号中启动数据传输到存储器和I / O数据总线，以减少任何给定时间的I / O引脚切换次数，从而降低噪声和功率在I / O引脚和系统中的消耗。

14. 发明授权

US06611900B2 System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model 有权
公开(公告)号：US06611900B2
公开(公告)日：2003-08-26
申请号：US10231087
申请日：2002-08-30
申请人： Rajesh Patel , Bryan D. Boatright , Larry Edward Thatcher
发明人： Rajesh Patel , Bryan D. Boatright , Larry Edward Thatcher
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F9/3004 , G06F9/30087
摘要： The present invention relates to locked memory instructions, and more specifically to a system and method for the high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model. In accordance with an embodiment of the present invention, a method for executing locked-memory instructions includes decoding a locked-memory instruction, obtaining exclusive ownership of a cacheline to be used by a load-lock operation, setting a bit to indicate the load-lock operation's ownership of the cacheline, and activating a snoop checking process. The method also includes modifying a load data value and storing the modified load data value. The method further includes determining that the cacheline is still exclusively owned, storing the load data value, determining that the cacheline is unsnooped, merging the modified load data value with the load data value, and releasing the locked-memory instruction to be retired.

15. 发明授权

US06490653B1 Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system 失效
标题翻译：用于根据数据处理系统中的推测性L2缓存命中来最优地发布依赖指令的方法和系统
公开(公告)号：US06490653B1
公开(公告)日：2002-12-03
申请号：US09325397
申请日：1999-06-03
申请人： Robert Alan Cargnoni , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
发明人： Robert Alan Cargnoni , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F1208
CPC分类号： G06F9/383 , G06F9/3842
摘要： A method for optimally issuing instructions that are related to a first instruction in a data processing system is disclosed. The processing system includes a primary and secondary cache. The method and system comprises speculatively indicating a hit of the first instruction in a secondary cache and releasing the dependent instructions. The method and system includes determining if the first instruction is within the secondary cache. The method and system further includes providing data related to the first instruction from the secondary cache to the primary cache when the instruction is within the secondary cache. A method and system in accordance with the present invention causes instructions that create dependencies (such as a load instruction) to signal an issue queue (which is responsible for issuing instructions with resolved conflicts) in advance, that the instruction will complete in a predetermined number of cycles. In an embodiment, a core interface unit (CIU) will signal an execution unit such as the Load Store Unit (LSU) that it is assumed that the instruction will hit in the L2 cache. An issue queue uses the signal to issue dependent instructions at an optimal time. If the instruction misses in the L2 cache, the cache hierarchy causes the instructions to be abandoned and re-executed when the data is available.
摘要翻译：公开了一种用于最佳地发出与数据处理系统中的第一指令相关的指令的方法。处理系统包括主缓存和二级缓存。所述方法和系统包括推测性地指示二次高速缓存中的第一指令的命中并释放依赖指令。该方法和系统包括确定第一指令是否在二级高速缓存内。所述方法和系统还包括当所述指令在所述辅助高速缓存内时，将与所述第二指令相关的数据提供给所述主缓存。根据本发明的方法和系统预先产生依赖性（诸如加载指令）的指令来发送发出队列（其负责发出具有解决的冲突的指令），指令将以预定数量完成的周期。在一个实施例中，核心接口单元（CIU）将向诸如加载存储单元（LSU）的执行单元发出信号，假定该指令将在L2高速缓存中命中。问题队列使用信号在最佳时间发出相关指令。如果L2缓存中的指令丢失，则缓存层次结构会导致在数据可用时放弃指令并重新执行指令。

16. 发明授权

US06425069B1 Optimization of instruction stream execution that includes a VLIW dispatch group 有权
标题翻译：优化包含VLIW调度组的指令流执行
公开(公告)号：US06425069B1
公开(公告)日：2002-07-23
申请号：US09263664
申请日：1999-03-05
申请人： Larry Edward Thatcher , John Edward Derrick
发明人： Larry Edward Thatcher , John Edward Derrick
IPC分类号： G06F1500
CPC分类号： G06F9/3853 , G06F9/3834
摘要： A method and system for optimizing execution of an instruction stream which includes a very long instruction word (VLIW) dispatch group in which ordering is not maintained is disclosed. The method and system comprises examining an access which initiated a flush operation; capturing an indice related to the flush operation; and causing all storage access instructions related to this indice to be dispatched as single-IOP groups until the indice is updated. Storage access to address space which is safe such as Guarded (G=1) or Direct Store (E=DS) must be handled in a non-speculative manner such that operations which could potentially go to volatile I/O devices or control locations that do not get processed out of order. Since the address is not known in the front end of the processor, this can only be determined by the load store unit or functional block which performs translation. Therefore, if a flush occurs for these conditions, in accordance with the present invention the value of the base register (RA) is latched and subsequent loads and stores which use this base register are decoded in a “safe” manner until an instruction is decoded which would change the base register value (safe means an internal instruction sequence which can be executed in order without repeating any accesses). The value of multiple base registers can be tracked in this manner, though the preferred embodiment would not use more than two, one of the base registers could be for input and one could be for output streams.
摘要翻译：公开了一种优化执行指令流的方法和系统，该方法和系统包括不维护顺序的非常长的指令字（VLIW）调度组。该方法和系统包括检查启动冲洗操作的访问; 捕获与冲洗操作相关的指示; 并将与此Indice相关的所有存储访问指令作为单IOP组发送，直到更新指示符。必须以不推测的方式来处理诸如保护（G = 1）或直接存储（E = DS）等安全的地址空间的存储访问，以使可能进入易失性I / O设备或控制位置的操作不要处理乱序。由于地址在处理器的前端是未知的，所以这只能由加载存储单元或执行翻译的功能块来确定。因此，如果对于这些条件发生冲突，根据本发明，基本寄存器（RA）的值被锁存，并且使用该基本寄存器的后续加载和存储以“安全”的方式被解码，直到指令被解码这将改变基址寄存器值（安全是指可以顺序执行而不重复任何访问的内部指令序列）。可以以这种方式跟踪多个基站寄存器的值，尽管优选实施例不会使用多于两个的基本寄存器中的一个可以用于输入，一个可以用于输出流。

17. 发明授权

US06338128B1 System and method for invalidating an entry in a translation unit 失效
标题翻译：使翻译单元中的条目无效的系统和方法
公开(公告)号：US06338128B1
公开(公告)日：2002-01-08
申请号：US09315543
申请日：1999-05-20
申请人： Albert Chang , Edward John Silha , Larry Edward Thatcher , Gus Wai-Yan Yeung
发明人： Albert Chang , Edward John Silha , Larry Edward Thatcher , Gus Wai-Yan Yeung
IPC分类号： G06F1200
CPC分类号： G06F12/1036 , G06F12/1054 , G06F12/109
摘要： As a program is replaced by the operating system running within a microprocessor, only those entries associated with the replaced program and resident within effective-to-real address translation units will be replaced. Those entries within the effective-to-real address translation units associated with the operating system and shared libraries, and any other software units operating within the microprocessor will not be invalidated.
摘要翻译：由于程序被微处理器内运行的操作系统所替代，所以仅替换与替换的程序相关联的入口和驻留在有效到实际地址转换单元内的条目。与操作系统和共享库相关联的有效到实际地址转换单元以及在微处理器内运行的任何其他软件单元之间的条目将不会被无效。

18. 发明授权

US6085289A Method and system for load data formatting and improved method for cache line organization 失效
标题翻译：负载数据格式化方法和系统，缓存线组织改进方法
公开(公告)号：US6085289A
公开(公告)日：2000-07-04
申请号：US896475
申请日：1997-07-18
申请人： Larry Edward Thatcher , John Beck , Michael Kevin Ciraula
发明人： Larry Edward Thatcher , John Beck , Michael Kevin Ciraula
IPC分类号： G06F9/312 , G06F12/08 , G06F12/00
CPC分类号： G06F9/30043 , G06F12/0886 , G06F9/3816
摘要： An improved load data formatter and methods for improving load data formatting and for cache line data organization are disclosed. The load data formatter includes a data selection mechanism, the data selection mechanism receiving a data cache line of a predetermined organization, and the data selection mechanism further supporting adjacent word swapping in the cache line. The load data formatter further includes at least two word selectors coupled to an output of the data selection mechanism, the at least two word selectors forming a doubleword on a chosen word boundary of the cache line. In a further aspect, the predetermined organization of the cache line is provided by grouping each corresponding bit of each byte in a cache line of data together, and expanding the grouping with an organization formed by one bit from a same byte within each word. The at least two word selectors may comprise even and odd multiplexers, and the load data formatter may also include splice registers, coupled to an output of one of the at least two selectors, which provide formatting of unaligned load access across a cache line boundary.
摘要翻译：公开了一种改进的负载数据格式化器和用于改进负载数据格式化和高速缓存行数据组织的方法。负载数据格式器包括数据选择机构，接收预定机构的数据高速缓存行的数据选择机构，以及进一步支持高速缓存行中相邻字交换的数据选择机制。负载数据格式化器还包括耦合到数据选择机构的输出的至少两个字选择器，所述至少两个字选择器在高速缓存线的所选字边界上形成双字。在另一方面，通过将数据的高速缓存行中的每个字节的每个相应位分组在一起来提供高速缓存行的预定组织，并且利用由每个单词内的相同字节由一位形成的组织来扩展分组。至少两个字选择器可以包括偶数和奇数多路复用器，并且负载数据格式化器还可以包括耦合到至少两个选择器中的一个的输出的拼接寄存器，其提供横跨高速缓存线边界的未对齐负载访问的格式化。

19. 发明授权

US6079002A Dynamic expansion of execution pipeline stages 失效
标题翻译：执行流水线阶段的动态扩展
公开(公告)号：US6079002A
公开(公告)日：2000-06-20
申请号：US935573
申请日：1997-09-23
申请人： Larry Edward Thatcher , John Stephen Muhich , Steven Wayne White , Troy Neal Hicks
发明人： Larry Edward Thatcher , John Stephen Muhich , Steven Wayne White , Troy Neal Hicks
IPC分类号： G06F9/38 , G06F12/00
CPC分类号： G06F9/3867 , G06F9/3824
摘要： A method and system in a data processing system for accessing information using an instruction specifying a memory address is disclosed. The method and system comprises issuing the instruction to an execution unit and storing an address derived from the specified address. The method and system also includes accessing a cache to obtain the information, using the derived address and determining, in response to a signal indicating that there has been a cache miss, if there is a location available to store the specified address in a queue. According to the system and method disclosed herein, the present invention allows for dynamic pipeline expansion of a processor without splitting this function between components depending upon the reason expansion was required, thereby increasing overall system performance.
摘要翻译：公开了一种使用指定存储器地址的指令访问信息的数据处理系统中的方法和系统。该方法和系统包括向执行单元发出指令并存储从指定地址导出的地址。该方法和系统还包括访问高速缓存以获得信息，使用导出的地址并且响应于指示已经存在高速缓存未命中的信号确定是否存在可用于将指定的地址存储在队列中的位置。根据本文公开的系统和方法，根据需要扩展的原因，本发明允许处理器的动态管道扩展，而不会在组件之间分离该功能，从而提高整体系统性能。

20. 发明授权

US06463511B2 System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model 有权
标题翻译：用于在具有分布式存储器和限制性存储器模型的系统中执行锁定存储器指令的高性能执行的系统和方法
公开(公告)号：US06463511B2
公开(公告)日：2002-10-08
申请号：US09750133
申请日：2000-12-29
申请人： Bryan D. Boatright , Rajesh Bhikhubhai Patel , Larry Edward Thatcher
发明人： Bryan D. Boatright , Rajesh Bhikhubhai Patel , Larry Edward Thatcher
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F9/3004 , G06F9/30087
摘要： The present invention relates to locked memory instructions, and more specifically to a system and method for the high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model. In accordance with an embodiment of the present invention, a method for executing locked-memory instructions includes decoding a locked-memory instruction, obtaining exclusive ownership of a cacheline to be used by a load-lock operation, setting a bit to indicate the load-lock operation's ownership of the cacheline, and activating a snoop checking process. The method also includes modifying a load data value and storing the modified load data value. The method further includes determining that the cacheline is still exclusively owned, storing the load data value, determining that the cacheline is unsnooped, merging the modified load data value with the load data value, and releasing the locked-memory instruction to be retired.
摘要翻译：本发明涉及锁定存储器指令，更具体地说涉及用于在具有分布式存储器和限制性存储器模型的系统中执行锁定存储器指令的高性能执行的系统和方法。根据本发明的实施例，一种用于执行锁定存储器指令的方法包括对锁定存储器指令进行解码，获得要通过加载锁定操作使用的高速缓存行的排他所有权，设置位以指示负载 - 锁定操作对高速缓存行的所有权，并激活侦听检查过程。该方法还包括修改负载数据值并存储修改的负载数据值。该方法还包括确定高速缓存行仍然是独占所有，存储加载数据值，确定高速缓存线不被播放，将修改的加载数据值与加载数据值合并，以及释放要退休的锁定存储器指令。

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