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1. 发明授权

US06490653B1 Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system 失效
标题翻译：用于根据数据处理系统中的推测性L2缓存命中来最优地发布依赖指令的方法和系统
公开(公告)号：US06490653B1
公开(公告)日：2002-12-03
申请号：US09325397
申请日：1999-06-03
申请人： Robert Alan Cargnoni , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
发明人： Robert Alan Cargnoni , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F1208
CPC分类号： G06F9/383 , G06F9/3842
摘要： A method for optimally issuing instructions that are related to a first instruction in a data processing system is disclosed. The processing system includes a primary and secondary cache. The method and system comprises speculatively indicating a hit of the first instruction in a secondary cache and releasing the dependent instructions. The method and system includes determining if the first instruction is within the secondary cache. The method and system further includes providing data related to the first instruction from the secondary cache to the primary cache when the instruction is within the secondary cache. A method and system in accordance with the present invention causes instructions that create dependencies (such as a load instruction) to signal an issue queue (which is responsible for issuing instructions with resolved conflicts) in advance, that the instruction will complete in a predetermined number of cycles. In an embodiment, a core interface unit (CIU) will signal an execution unit such as the Load Store Unit (LSU) that it is assumed that the instruction will hit in the L2 cache. An issue queue uses the signal to issue dependent instructions at an optimal time. If the instruction misses in the L2 cache, the cache hierarchy causes the instructions to be abandoned and re-executed when the data is available.
摘要翻译：公开了一种用于最佳地发出与数据处理系统中的第一指令相关的指令的方法。处理系统包括主缓存和二级缓存。所述方法和系统包括推测性地指示二次高速缓存中的第一指令的命中并释放依赖指令。该方法和系统包括确定第一指令是否在二级高速缓存内。所述方法和系统还包括当所述指令在所述辅助高速缓存内时，将与所述第二指令相关的数据提供给所述主缓存。根据本发明的方法和系统预先产生依赖性（诸如加载指令）的指令来发送发出队列（其负责发出具有解决的冲突的指令），指令将以预定数量完成的周期。在一个实施例中，核心接口单元（CIU）将向诸如加载存储单元（LSU）的执行单元发出信号，假定该指令将在L2高速缓存中命中。问题队列使用信号在最佳时间发出相关指令。如果L2缓存中的指令丢失，则缓存层次结构会导致在数据可用时放弃指令并重新执行指令。

2. 发明申请

US20100268882A1 LOAD REQUEST SCHEDULING IN A CACHE HIERARCHY 有权
标题翻译：缓存中的加载请求调度
公开(公告)号：US20100268882A1
公开(公告)日：2010-10-21
申请号：US12424207
申请日：2009-04-15
申请人： Robert Alan Cargnoni , Guy Lynn Guthrie , Stephen James Powell , William John Starke , Jeffrey A. Stuecheli
发明人： Robert Alan Cargnoni , Guy Lynn Guthrie , Stephen James Powell , William John Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/123 , G06F12/084 , G06F12/0897
摘要： A system and method for tracking core load requests and providing arbitration and ordering of requests. When a core interface unit (CIU) receives a load operation from the processor core, a new entry in allocated in a queue of the CIU. In response to allocating the new entry in the queue, the CIU detects contention between the load request and another memory access request. In response to detecting contention, the load request may be suspended until the contention is resolved. Received load requests may be stored in the queue and tracked using a least recently used (LRU) mechanism. The load request may then be processed when the load request resides in a least recently used entry in the load request queue. CIU may also suspend issuing an instruction unless a read claim (RC) machine is available. In another embodiment, CIU may issue stored load requests in a specific priority order.
摘要翻译：用于跟踪核心负载请求并提供仲裁和请求排序的系统和方法。当核心接口单元（CIU）从处理器核心接收到加载操作时，分配在CIU队列中的新条目。响应于在队列中分配新条目，CIU检测加载请求和另一个存储器访问请求之间的争用。响应于检测到争用，负载请求可以被暂停，直到争用被解决。接收到的加载请求可以存储在队列中，并使用最近最少使用的（LRU）机制进行跟踪。然后可以在加载请求驻留在加载请求队列中最近最少使用的条目中时处理加载请求。除非读取权利要求（RC）机器可用，否则CIU也可以暂停发出指令。在另一个实施例中，CIU可以以特定优先级顺序发布存储的加载请求。

3. 发明授权

US07493417B2 Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system 失效
标题翻译：用于在多处理器系统中使用处理器互连的微处理器通信的方法和数据处理系统
公开(公告)号：US07493417B2
公开(公告)日：2009-02-17
申请号：US10318515
申请日：2002-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/16
CPC分类号： G06F15/167
摘要： Processor communication registers (PCRs) contained in each processor within a multiprocessor system and interconnected by a specialized bus provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs utilizing communication over the specialized bus, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：处理器通信寄存器（PCR）包含在多处理器系统中的每个处理器中并由专用总线互连提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。每个处理器利用专用总线上的通信在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据内的变化，并绕过高速缓存子系统。通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率无限流的加载，存储和无效命令。

4. 发明授权

US07089364B2 System and method to stall dispatch of gathered store operations in a store queue using a timer 失效
标题翻译：使用定时器将存储队列中收集的存储操作分派的系统和方法停止
公开(公告)号：US07089364B2
公开(公告)日：2006-08-08
申请号：US10825188
申请日：2004-04-15
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Hugh Shen , Derek Edward Williams
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Hugh Shen , Derek Edward Williams
IPC分类号： G06F12/12
CPC分类号： G06F12/0897 , G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F12/0804
摘要： A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.
摘要翻译：一种方法和处理器系统，其基本上增强了存储队列条目的存储收集能力，以便能够在该条目被选择用于发送之前收集最大数量的接近时间存储操作。为每个条目提供一个计数器，以跟踪从上次收集到条目的时间。当计数器达到阈值饱和点之前没有发生新的聚合时，该信号将被发出准备就绪。通过在计数器到期之前定义最佳阈值饱和点，为入口提供足够的时间来收集即时存储操作。当某些条件发生时，该条目可能被视为有资格进行选择，包括条目变满，发出屏障操作和计数器饱和。计数器的使用增加了存储队列条目完成收集足够的存储操作以在将该条目分派到RC机器之前更新整个高速缓存行的能力。

5. 发明授权

US07055002B2 Integrated purge store mechanism to flush L2/L3 cache structure for improved reliabity and serviceability 有权
标题翻译：集成的清除存储机制来刷新L2 / L3缓存结构，以提高可靠性和可维护性
公开(公告)号：US07055002B2
公开(公告)日：2006-05-30
申请号：US10424486
申请日：2003-04-25
申请人： Robert Alan Cargnoni , Guy Lynn Guthrie , Kevin Franklin Reick , Derek Edward Williams
发明人： Robert Alan Cargnoni , Guy Lynn Guthrie , Kevin Franklin Reick , Derek Edward Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F12/0897
摘要： A method of reducing errors in a cache memory of a computer system (e.g., an L2 cache) by periodically issuing a series of purge commands to the L2 cache, sequentially flushing cache lines from the L2 cache to an L3 cache in response to the purge commands, and correcting errors (single-bit) in the cache lines as they are flushed to the L3 cache. Purge commands are issued only when the processor cores associated with the L2 cache have an idle cycle available in a store pipe to the cache. The flush rate of the purge commands can be programmably set, and the purge mechanism can be implemented either in software running on the computer system, or in hardware integrated with the L2 cache. In the case of the software, the purge mechanism can be incorporated into the operating system. In the case of hardware, a purge engine can be provided which advantageously utilizes the store pipe that is provided between the L1 and L2 caches. The L2 cache can be forced to victimize cache lines, by setting tag bits for the cache lines to a value that misses in the L2 cache (e.g., cache-inhibited space). With the eviction mechanism of the cache placed in a direct-mapped mode, the address misses will result in eviction of the cache lines, thereby flushing them to the L3 cache.
摘要翻译：通过周期性地向L2高速缓存发出一系列清除命令来减少计算机系统（例如，L2高速缓存）的高速缓冲存储器中的错误的方法，响应于清除，将缓存行从L2高速缓存刷新到L3高速缓存命令和纠正高速缓存行中的错误（单位），因为它们被刷新到L3高速缓存。清除命令仅在与L2缓存关联的处理器核心具有可用于缓存的存储管道中的空闲周期时发出。清除命令的刷新速率可以可编程设置，并且清除机制可以在计算机系统上运行的软件中，也可以在与L2缓存集成的硬件中实现。在软件的情况下，可以将清除机构并入操作系统。在硬件的情况下，可以提供有利地利用设置在L1和L2高速缓存之间的存储管道的清洗引擎。通过将高速缓存行的标记位设置为L2高速缓存中缺少的值（例如，禁止高速缓存的空间），L2高速缓存可能被迫使高速缓存行受害。由于高速缓存的驱逐机制处于直接映射模式，地址未命中将导致高速缓存线的驱逐，从而将它们刷新到L3高速缓存。

6. 发明授权

US07047320B2 Data processing system providing hardware acceleration of input/output (I/O) communication 有权
标题翻译：数据处理系统提供输入/输出（I / O）通讯的硬件加速
公开(公告)号：US07047320B2
公开(公告)日：2006-05-16
申请号：US10339724
申请日：2003-01-09
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F3/00
CPC分类号： G06F13/124 , G06F12/0835
摘要： An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication between the processor core and a system interconnect external to the integrated circuit, and at least a portion of an external communication adapter, coupled to the processor core, that supports input/output communication via an input/output communication link.
摘要翻译：诸如处理单元的集成电路包括衬底和形成在衬底中的集成电路。集成电路包括执行指令的处理器核心，耦合到处理器核心的互连接口，其支持处理器核心与集成电路外部的系统互连之间的通信，以及外部通信适配器的至少一部分，耦合通过输入/输出通信链路支持输入/输出通信的处理器核心。

7. 发明授权

US07818364B2 Method and data processing system for microprocessor communication in a cluster-based multi-processor system 失效
标题翻译：基于群集的多处理器系统中微处理器通信的方法和数据处理系统
公开(公告)号：US07818364B2
公开(公告)日：2010-10-19
申请号：US11952479
申请日：2007-12-07
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/76 , G06F15/163
CPC分类号： H04L69/16 , G06F15/17 , H04L12/42 , H04L67/1002 , H04L69/161 , H04W28/14
摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存行，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

8. 发明授权

US07356568B2 Method, processing unit and data processing system for microprocessor communication in a multi-processor system 失效
标题翻译：用于多处理器系统中微处理器通信的方法，处理单元和数据处理系统
公开(公告)号：US07356568B2
公开(公告)日：2008-04-08
申请号：US10318514
申请日：2002-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F13/00
CPC分类号： G06F9/30101
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器系统内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。每个处理器在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率无限流的加载，存储和无效命令。

9. 发明授权

US07069494B2 Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism 有权
标题翻译：在ECC保护机制中应用特殊ECC矩阵解决卡位故障
公开(公告)号：US07069494B2
公开(公告)日：2006-06-27
申请号：US10418549
申请日：2003-04-17
申请人： Robert Alan Cargnoni , Guy Lynn Guthrie , Kirk Samuel Livingston , William John Starke
发明人： Robert Alan Cargnoni , Guy Lynn Guthrie , Kirk Samuel Livingston , William John Starke
IPC分类号： H03M13/11
CPC分类号： G06F11/1064 , H03M13/13
摘要： A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N−1)-bit error detection. In the illustrative embodiment, the ECC matrix has an odd number of bits set in each row thereof. In the case of an ECC protected mechanism such as a memory device, these properties facilitate the use of an inversion bit for correcting hard faults in the stored data. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array. The corresponding inversion bit for this entry is accordingly set to indicate that the data as currently stored is inverted. Thereafter, the data is re-read from the array, and if the error was due to a hard fault (stuck bit), it will appear correct (after applying the polarity indicated by the inversion bit), since the inversion will have changed the value of the defective bit to the stuck value. The inversion bit may be part of the data itself. In this case, one of the columns in the ECC matrix corresponds to the inversion bit, and each bit in that column of the matrix is set. In the case of an ECC protected mechanism such as a system bus, once a stuck bit condition is detected, the sending device can elect to send data such that the polarity of the data for that bit is always flipped to match the logic level of the stuck value on the wire. This approach allows for full single-bit correct, double-bit detect even in the presence of a stuck bit.
摘要翻译：一种通过将具有多个位N的数据应用于纠错码（ECC）矩阵来校正诸如高速缓存或系统总线的计算机系统的ECC保护机制中的错误的方法，以产生错误检测综合征，其中 ECC矩阵具有多个行和列，给定列对应于相应的一个数据位，并且所选择的位在每个列和每行的ECC矩阵中被设置，使得对于ECC矩阵的编码允许N位纠错和（N-1）位错误检测。在说明性实施例中，ECC矩阵在其每行中设置奇数位。在诸如存储器件的ECC保护机制的情况下，这些属性有利于使用反转位来校正所存储的数据中的硬故障。当检测到错误并且在其被校正之后，校正的数据被反转，然后被重写到高速缓存阵列。因此，该条目的相应的反转位被设置为指示当前存储的数据被反转。此后，数据从阵列重新读取，如果错误是由于硬故障（卡位）引起的，则会显示正确的（应用反转位指示的极性后），因为反转将会改变有缺陷位的值到卡住值。反转位可能是数据本身的一部分。在这种情况下，ECC矩阵中的列之一对应于反转比特，矩阵的该列中的每个比特被设置。在诸如系统总线的ECC保护机制的情况下，一旦检测到卡位状态，发送设备就可以选择发送数据，使得该位的数据的极性总是被翻转以匹配在线上卡住了值。这种方法允许完全单位正确，双位检测，即使存在卡位。

10. 发明授权

US07039832B2 Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems 失效
标题翻译：稳定的系统可靠性通过收缩制造级芯片测试在微处理器/系统上的实时操作
公开(公告)号：US07039832B2
公开(公告)日：2006-05-02
申请号：US10313329
申请日：2002-12-05
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A method and system are disclosed for running a manufacturing-level test program on an installed processor by interrupting processor execution of a non-test process. Periodic execution of the manufacturing-level test program allows the processor to continually self-test during normal function operation, in order to facilitate proper maintenance and function of the processor and a data processing system of which the processor is a part.
摘要翻译：公开了一种方法和系统，用于通过中断非测试过程的处理器执行来在安装的处理器上运行制造级测试程序。制造级测试程序的定期执行允许处理器在正常功能操作期间不间断地进行自检，以便促进处理器和处理器作为其一部分的数据处理系统的适当维护和功能。

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