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1. 发明授权

US06463511B2 System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model 有权
标题翻译：用于在具有分布式存储器和限制性存储器模型的系统中执行锁定存储器指令的高性能执行的系统和方法
公开(公告)号：US06463511B2
公开(公告)日：2002-10-08
申请号：US09750133
申请日：2000-12-29
申请人： Bryan D. Boatright , Rajesh Bhikhubhai Patel , Larry Edward Thatcher
发明人： Bryan D. Boatright , Rajesh Bhikhubhai Patel , Larry Edward Thatcher
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F9/3004 , G06F9/30087
摘要： The present invention relates to locked memory instructions, and more specifically to a system and method for the high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model. In accordance with an embodiment of the present invention, a method for executing locked-memory instructions includes decoding a locked-memory instruction, obtaining exclusive ownership of a cacheline to be used by a load-lock operation, setting a bit to indicate the load-lock operation's ownership of the cacheline, and activating a snoop checking process. The method also includes modifying a load data value and storing the modified load data value. The method further includes determining that the cacheline is still exclusively owned, storing the load data value, determining that the cacheline is unsnooped, merging the modified load data value with the load data value, and releasing the locked-memory instruction to be retired.
摘要翻译：本发明涉及锁定存储器指令，更具体地说涉及用于在具有分布式存储器和限制性存储器模型的系统中执行锁定存储器指令的高性能执行的系统和方法。根据本发明的实施例，一种用于执行锁定存储器指令的方法包括对锁定存储器指令进行解码，获得要通过加载锁定操作使用的高速缓存行的排他所有权，设置位以指示负载 - 锁定操作对高速缓存行的所有权，并激活侦听检查过程。该方法还包括修改负载数据值并存储修改的负载数据值。该方法还包括确定高速缓存行仍然是独占所有，存储加载数据值，确定高速缓存线不被播放，将修改的加载数据值与加载数据值合并，以及释放要退休的锁定存储器指令。

2. 发明授权

US06678807B2 System and method for multiple store buffer forwarding in a system with a restrictive memory model 有权
标题翻译：具有限制性内存模型的系统中多存储缓冲区转发的系统和方法
公开(公告)号：US06678807B2
公开(公告)日：2004-01-13
申请号：US09740803
申请日：2000-12-21
申请人： Bryan D. Boatright , Rajesh Patel , Larry Edward Thatcher
发明人： Bryan D. Boatright , Rajesh Patel , Larry Edward Thatcher
IPC分类号： G06F1200
CPC分类号： G06F9/3826 , G06F9/3834
摘要： The present invention relates to the use of multiple store buffer forwarding in a microprocessor system with a restrictive memory model. In accordance with an embodiment of the present invention, the system and method allow load operations that are completely covered by two or more store operations to receive data via store buffer forwarding in such a manner as to retain the side effects of the restrictive memory model thereby increasing processor performance without violating the restrictive memory model. In accordance with an embodiment the present invention, a method for multiple store buffer forwarding in a system with a restrictive memory model includes executing multiple store instructions, executing a load instruction, determining that a memory region addressed by the load instruction matches a cacheline address in a memory, determining that data stored by the multiple store instructions completely covers the memory region addressed by the load instruction, and transmitting a store forward is OK signal.
摘要翻译：本发明涉及在具有限制性存储器模型的微处理器系统中使用多存储缓冲器转发。根据本发明的实施例，系统和方法允许由两个或多个存储操作完全覆盖的加载操作以经由存储缓冲器转发来接收数据，从而保持限制性存储器模型的副作用提高处理器性能而不违反限制性内存模式。根据本发明的实施例，一种用于具有限制性存储器模型的系统中的多存储缓冲器转发的方法包括执行多个存储指令，执行加载指令，确定由加载指令寻址的存储器区域与缓存线地址匹配存储器，确定由多个存储指令存储的数据完全覆盖由加载指令寻址的存储器区域，并且向前发送存储区是OK信号。

3. 发明授权

US06611900B2 System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model 有权
公开(公告)号：US06611900B2
公开(公告)日：2003-08-26
申请号：US10231087
申请日：2002-08-30
申请人： Rajesh Patel , Bryan D. Boatright , Larry Edward Thatcher
发明人： Rajesh Patel , Bryan D. Boatright , Larry Edward Thatcher
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F9/3004 , G06F9/30087
摘要： The present invention relates to locked memory instructions, and more specifically to a system and method for the high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model. In accordance with an embodiment of the present invention, a method for executing locked-memory instructions includes decoding a locked-memory instruction, obtaining exclusive ownership of a cacheline to be used by a load-lock operation, setting a bit to indicate the load-lock operation's ownership of the cacheline, and activating a snoop checking process. The method also includes modifying a load data value and storing the modified load data value. The method further includes determining that the cacheline is still exclusively owned, storing the load data value, determining that the cacheline is unsnooped, merging the modified load data value with the load data value, and releasing the locked-memory instruction to be retired.

4. 发明授权

US07197670B2 Methods and apparatuses for reducing infant mortality in semiconductor devices utilizing static random access memory (SRAM) 失效
标题翻译：利用静态随机存取存储器（SRAM）降低半导体器件婴儿死亡率的方法和装置
公开(公告)号：US07197670B2
公开(公告)日：2007-03-27
申请号：US10750562
申请日：2003-12-31
申请人： Bryan D. Boatright , Ben J. Eapen , C. Glenn Shirley , Carl Scafidi
发明人： Bryan D. Boatright , Ben J. Eapen , C. Glenn Shirley , Carl Scafidi
IPC分类号： G06F11/00
CPC分类号： G06F12/126 , G06F11/073 , G06F11/0751 , G06F11/0793 , G06F11/1048 , G06F2212/1032
摘要： In accordance with various embodiments of the present invention, a cache-equipped semi-conductor device is provided with enhanced error detection logic to detect a first location-independent error within an area of the cache memory and prevent further use of the area if the error is determined to be the second consecutive error associated with a common area.
摘要翻译：根据本发明的各种实施例，具有高速缓存的半导体器件被提供有增强的错误检测逻辑，以检测高速缓存存储器的区域内的第一位置无关错误，并防止如果错误进一步使用该区域被确定为与公共区域相关联的第二连续错误。

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