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1. 发明授权

US06490653B1 Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system 失效
标题翻译：用于根据数据处理系统中的推测性L2缓存命中来最优地发布依赖指令的方法和系统
公开(公告)号：US06490653B1
公开(公告)日：2002-12-03
申请号：US09325397
申请日：1999-06-03
申请人： Robert Alan Cargnoni , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
发明人： Robert Alan Cargnoni , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F1208
CPC分类号： G06F9/383 , G06F9/3842
摘要： A method for optimally issuing instructions that are related to a first instruction in a data processing system is disclosed. The processing system includes a primary and secondary cache. The method and system comprises speculatively indicating a hit of the first instruction in a secondary cache and releasing the dependent instructions. The method and system includes determining if the first instruction is within the secondary cache. The method and system further includes providing data related to the first instruction from the secondary cache to the primary cache when the instruction is within the secondary cache. A method and system in accordance with the present invention causes instructions that create dependencies (such as a load instruction) to signal an issue queue (which is responsible for issuing instructions with resolved conflicts) in advance, that the instruction will complete in a predetermined number of cycles. In an embodiment, a core interface unit (CIU) will signal an execution unit such as the Load Store Unit (LSU) that it is assumed that the instruction will hit in the L2 cache. An issue queue uses the signal to issue dependent instructions at an optimal time. If the instruction misses in the L2 cache, the cache hierarchy causes the instructions to be abandoned and re-executed when the data is available.
摘要翻译：公开了一种用于最佳地发出与数据处理系统中的第一指令相关的指令的方法。处理系统包括主缓存和二级缓存。所述方法和系统包括推测性地指示二次高速缓存中的第一指令的命中并释放依赖指令。该方法和系统包括确定第一指令是否在二级高速缓存内。所述方法和系统还包括当所述指令在所述辅助高速缓存内时，将与所述第二指令相关的数据提供给所述主缓存。根据本发明的方法和系统预先产生依赖性（诸如加载指令）的指令来发送发出队列（其负责发出具有解决的冲突的指令），指令将以预定数量完成的周期。在一个实施例中，核心接口单元（CIU）将向诸如加载存储单元（LSU）的执行单元发出信号，假定该指令将在L2高速缓存中命中。问题队列使用信号在最佳时间发出相关指令。如果L2缓存中的指令丢失，则缓存层次结构会导致在数据可用时放弃指令并重新执行指令。

2. 发明授权

US06336168B1 System and method for merging multiple outstanding load miss instructions 有权
标题翻译：用于合并多个未完成的负载错误指令的系统和方法
公开(公告)号：US06336168B1
公开(公告)日：2002-01-01
申请号：US09259139
申请日：1999-02-26
申请人： Marlin Wayne Frederick, Jr. , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
发明人： Marlin Wayne Frederick, Jr. , Bruce Joseph Ronchetti , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F1316
CPC分类号： G06F9/30043 , G06F9/3824
摘要： Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.
摘要翻译：在加载存储单元中执行多个加载指令的流水线和并行执行。当第一个加载指令引起高速缓存未命中并继续从系统存储器层次结构检索加载数据时，寻址相同加载数据的第二加载指令将被合并到第一加载指令中，以便从系统内存层次结构返回的数据为发送到注册与第一和第二加载指令相关联的文件。结果，第二加载指令不必等待，直到在数据高速缓存中写入和验证加载数据。

3. 发明授权

US06237081B1 Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor 失效
标题翻译：排队方法和装置，用于便于在处理器中拒绝顺序指令
公开(公告)号：US06237081B1
公开(公告)日：2001-05-22
申请号：US09213319
申请日：1998-12-16
申请人： Hung Qui Le , Larry Edward Thatcher , Bruce Joseph Ronchetti , David James Shippy
发明人： Hung Qui Le , Larry Edward Thatcher , Bruce Joseph Ronchetti , David James Shippy
IPC分类号： G06F932
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861
摘要： A processor (100) includes an issue unit (125) having an issue queue (144) for issuing instructions to an execution unit (140). The execution unit (140) may accept and execute the instruction or produce a reject signal. After each instruction is issued, the issue queue (144) retains the issued instruction for a critical period. After the critical period, the issue queue (144) may drop the issued instruction unless the execution unit (140) has generated a reject signal. If the execution unit (140) has generated a reject signal, the instruction is eventually marked in the issue queue (144) as being available to be reissued. The length of time that the rejected instruction is held from reissue may be modified depending upon the nature of the rejection by the execution unit (140). Also, the execution unit (140) may conduct corrective actions in response to certain reject conditions so that the instruction may be fully executed upon reissue.
摘要翻译：处理器（100）包括具有用于向执行单元（140）发出指令的发布队列（144）的发布单元（125）。执行单元（140）可接受并执行该指令或产生拒绝信号。在发出每条指令之后，发出队列（144）保留发出的关键周期指令。在关键时段之后，发布队列（144）可以放弃发出的指令，除非执行单元（140）已经产生了拒绝信号。如果执行单元（140）已经产生了拒绝信号，则指令最终在发布队列（144）中被标记为可重新发行。可以根据执行单元（140）的拒绝的性质来修改拒绝指令从重新发行保持的时间长度。此外，执行单元（140）可以响应于某些拒绝条件进行校正动作，使得可以在重新发布时完全执行该指令。

4. 发明授权

US06266768B1 System and method for permitting out-of-order execution of load instructions 失效
标题翻译：允许无序执行加载指令的系统和方法
公开(公告)号：US06266768B1
公开(公告)日：2001-07-24
申请号：US09213323
申请日：1998-12-16
申请人： Marlin Wayne Frederick, Jr. , Bruce Joseph Ronchetti , Larry Edward Thatcher
发明人： Marlin Wayne Frederick, Jr. , Bruce Joseph Ronchetti , Larry Edward Thatcher
IPC分类号： G06F738
CPC分类号： G06F9/3834
摘要： In a load/store unit within a microprocessor, load instructions are executed out of order. The load instructions are assigned tags in a predetermined manner, and then assigned to a load reorder queue for keeping track of the program order of the load instructions. Then when new load instructions are issued, the new load instructions are compared to entries within the load reorder queues to detect out of order problems.
摘要翻译：在微处理器内的加载/存储单元中，加载指令按顺序执行。加载指令以预定方式分配标签，然后分配给负载重新排序队列，以跟踪加载指令的程序顺序。然后当发出新的加载指令时，将新的加载指令与加载重新排序队列中的条目进行比较，以检测出乱序问题。

5. 发明授权

US06301654B1 System and method for permitting out-of-order execution of load and store instructions 有权
标题翻译：允许无序执行加载和存储指令的系统和方法
公开(公告)号：US06301654B1
公开(公告)日：2001-10-09
申请号：US09213331
申请日：1998-12-16
申请人： Bruce Joseph Ronchetti , Dave Shippy , Larry Edward Thatcher
发明人： Bruce Joseph Ronchetti , Dave Shippy , Larry Edward Thatcher
IPC分类号： G06F738
CPC分类号： G06F9/30043 , G06F9/3834 , G06F9/3842
摘要： In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. Then when new load or store instructions are issued, the new load or store instructions are compared to entries within the load and store reorder queues to detect out of order problems.
摘要翻译：在微处理器内的加载/存储单元中，加载和存储指令是无序执行的。加载和存储指令以预定方式分配标签，然后分配给加载和存储重新排序队列，以跟踪加载和存储指令的程序顺序。然后，当发出新的加载或存储指令时，将新的加载或存储指令与加载和存储重新排序队列中的条目进行比较，以检测出乱序问题。

6. 发明授权

US06349382B1 System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order 失效
标题翻译：用于存储转发的系统为组分配负载和存储指令，并重新排序队列以跟踪程序顺序
公开(公告)号：US06349382B1
公开(公告)日：2002-02-19
申请号：US09263665
申请日：1999-03-05
申请人： Kurt Alan Feiste , Bruce Joseph Ronchetti , David James Shippy
发明人： Kurt Alan Feiste , Bruce Joseph Ronchetti , David James Shippy
IPC分类号： G06F1500
CPC分类号： G06F9/3834 , G06F9/3824
摘要： In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. When a load instruction is issued for execution, a determination is made whether the load instruction is attempting to load data to a memory location that is the same as a previously executed store instruction is waiting to complete. If so, then the data waiting to be stored within the cache by the store instruction is directly forwarded to the load instruction.
摘要翻译：在微处理器内的加载/存储单元中，加载和存储指令是无序执行的。加载和存储指令以预定方式分配标签，然后分配给加载和存储重新排序队列，以跟踪加载和存储指令的程序顺序。当执行加载指令时，确定加载指令是否试图将数据加载到与先前执行的存储指令正在等待完成的存储单元相同的存储单元。如果是这样，则通过存储指令等待存储在高速缓存内的数据被直接转发到加载指令。

7. 发明申请

US20100262808A1 MANAGING INSTRUCTIONS FOR MORE EFFICIENT LOAD/STORE UNIT USAGE 有权
标题翻译：管理更有效的装载/存储单元使用说明
公开(公告)号：US20100262808A1
公开(公告)日：2010-10-14
申请号：US12420143
申请日：2009-04-08
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3824 , G06F9/3836 , G06F11/348 , G06F2201/88 , Y02D10/34
摘要： The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.
摘要翻译：本文描述的说明性实施例提供了一种计算机实现的方法，装置和用于管理指令的系统。加载/存储单元在端口接收第一条指令。响应于确定第一指令具有第一拒绝条件，加载/存储单元拒绝第一指令。然后，指令排序单元响应于加载/存储单元来激活第一位以拒绝第一指令。当第一位被激活时，指令排序单元阻止重新发行的第一条指令。处理器单元确定第一指令的拒绝类。指令排序单元启动定时器。定时器的长度取决于第一条指令的拒绝类型。指令排序单元重置响应定时器超时的第一位。响应于重置第一位，指令排序单元允许第一指令变得有资格重新发行。

8. 发明授权

US06640293B1 Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays 有权
标题翻译：利用别名命中信号检测真实地址标签阵列内的错误的装置和方法
公开(公告)号：US06640293B1
公开(公告)日：2003-10-28
申请号：US09624105
申请日：2000-07-24
申请人： Jose Angel Paredes , Bruce Joseph Ronchetti , Binta Minesh Patel , George McNeil Lattimore
发明人： Jose Angel Paredes , Bruce Joseph Ronchetti , Binta Minesh Patel , George McNeil Lattimore
IPC分类号： G06F1200
CPC分类号： G06F11/0751 , G06F11/0772 , G06F11/0781 , G06F12/1063
摘要： A data processing system including a processor having a load/store unit and method for utilizing alias hit signals to detect errors within the read address tag arrays. Within a load store unit, implemented within a processor, a real address tag array is utilized to indicate when effective address aliasing occurs in a primary cache array. If aliasing occurs, Alias Hit signals are then used to clear any aliased entries. These Alias Hit signals can also be utilized to determine if there has been some type of failure within the real address tag array.
摘要翻译：一种数据处理系统，包括具有加载/存储单元的处理器和用于利用别名命中信号来检测读取地址标签阵列内的错误的方法。在处理器内实现的加载存储单元中，使用实际地址标签阵列来指示当主缓存阵列中发生有效的地址混叠时。如果出现混叠，则使用别名命中信号来清除任何别名条目。这些别名命中信号也可用于确定真实地址标签阵列中是否存在某种类型的故障。

9. 发明授权

US06178497B1 System and method for determining the relative age of instructions in a processor 失效
标题翻译：用于确定处理器中的指令的相对年龄的系统和方法
公开(公告)号：US06178497B1
公开(公告)日：2001-01-23
申请号：US09134342
申请日：1998-08-14
申请人： Marlin Wayne Frederick, Jr. , Bruce Joseph Ronchetti , Cang Tran
发明人： Marlin Wayne Frederick, Jr. , Bruce Joseph Ronchetti , Cang Tran
IPC分类号： G06F930
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A system and method for determining an age function by performing a logical function on each entry residing within a queue, determining when a particular one of the entries residing in the queue was stored in the queue relative to the other entries, and determining an oldest or youngest entry residing in the queue relative to the logical functions performed on each of the instructions. In one embodiment of the present invention, the entries are instructions temporarily stored within a queue in the processor. The logical function performed may determine which of the instructions is valid. The queue may be cyclical.
摘要翻译：一种用于通过对驻留在队列中的每个条目执行逻辑功能来确定年龄功能的系统和方法，确定驻留在队列中的特定一个条目何时相对于其他条目存储在队列中，并且确定最旧的或相对于在每个指令上执行的逻辑功能，居住在队列中的最小条目。在本发明的一个实施例中，条目是临时存储在处理器中的队列内的指令。执行的逻辑功能可以确定哪些指令是有效的。队列可能是周期性的。

10. 发明申请

US20100180081A1 Adaptive Data Prefetch System and Method 失效
标题翻译：自适应数据预取系统和方法
公开(公告)号：US20100180081A1
公开(公告)日：2010-07-15
申请号：US12354219
申请日：2009-01-15
申请人： Pradip Bose , Alper Buyuktosunoglu , Miles Robert Dooley , Michael Stephen Floyd , David Scott Ray , Bruce Joseph Ronchetti
发明人： Pradip Bose , Alper Buyuktosunoglu , Miles Robert Dooley , Michael Stephen Floyd , David Scott Ray , Bruce Joseph Ronchetti
IPC分类号： G06F12/08 , G06F1/32 , G06F12/00
CPC分类号： G06F12/0862 , G06F1/3203 , G06F12/0897 , G06F2212/6022
摘要： A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds.
摘要翻译：数据处理系统包括处理器，包括多级缓存，预取系统和存储器的单元。数据处理系统可以在第一模式和第二模式中操作。预取系统可以响应于由外部代理设置的所需功耗策略或基于片上功率/性能阈值的硬件自动地改变行为。

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